LowK wafer dicing robustness considerations and laser grooving process selection

Patrick Laurent, O. Robin, B. Bouillard
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引用次数: 3

Abstract

Zero defect in semiconductor packaging is key especially for high demanding reliability applications (automotive, spatial…) combined with high performance technologies (Silicon ultra lowK wafers 40nm and beyond). The most complex challenge is the Chip Package Interconnect which requires an optimized and controlled singulation process to prevent weaknesses occurring during the process (ILD crack/ delamination, side wall crack, metal burrs, humidity propagation and die strength weakness). Laser grooving prior mechanical dicing offers a good seal ring protection of the chips, ie use of a laser to perform ablation and remove the sawing street contents (dielectric / metallization / patterns) in order to make a clean ‘path’ for the mechanical sawing step afterward. Degradation of the blade condition is also reduced with this approach. This article describes the interactions between laser grooving process and the lLD BEOL delamination prevention by applying a perfect U shape profile.Laser Grooving process selection is a complex combination of different requirements: (i) U shape profile geometry tradeoff to guarantee integrity of BEOL layers during mechanical dicing, while keeping a high level of miniaturization of the sawing street not to increase wafer cost. (ii) Laser technology and process to match the required U-shape geometry minimizing redeposition of residues (recast), avoid pitting (voids) and absorb the heterogenous content of a scribe line with a minimum level of energy applied. This is achieved thanks to an accurate selection of the laser source (wavelength, beam size), accuracy of the beam position (lens optical system), ablation method (multi pass) and process parameter optimization (power, speed, frequency…). (iii) Advanced characterization technics are required to ensure the required quality criteria are matched, like 3D profilometer, FIB cross sections, SEM controls, AOI and 3 points die strength.STMicroelectronics is deploying this quality driven mindset to high volume manufacturing environment in all BE manufacturing plants. Emerging technologies like ultrafast laser wavelength or replacement of mechanical dicing by plasma dicing are next steps of interest further enhanced the robustness of more and more fragile wafer FE technologies.
LowK晶圆切割稳健性考虑及激光开槽工艺选择
半导体封装中的零缺陷是关键,特别是对于高要求的可靠性应用(汽车,空间…)结合高性能技术(硅超低k晶圆40nm及以上)。最复杂的挑战是芯片封装互连,它需要一个优化和控制的模拟过程,以防止在过程中出现弱点(ILD裂纹/分层,侧壁裂纹,金属毛刺,湿度传播和模具强度弱点)。在机械切割之前,激光开槽为切屑提供了良好的密封圈保护,即使用激光进行烧蚀并去除锯切过程中的内容物(电介质/金属化/图案),以便为随后的机械锯切步骤创造一条干净的“路径”。这种方法也减少了叶片状况的退化。本文描述了激光开槽工艺与应用完美U型轮廓防止lLD BEOL分层之间的相互作用。激光切槽工艺选择是不同要求的复杂组合:(i)在机械切割过程中权衡U形轮廓几何形状,以保证BEOL层的完整性,同时保持锯街的高度小型化,不增加晶圆成本。(ii)符合所需u形几何形状的激光技术和工艺,最大限度地减少残留物的再沉积(重铸),避免点蚀(空洞),并以最小的能量吸收划线线的异质内容。这要归功于准确选择激光源(波长、光束尺寸)、光束位置的准确性(透镜光学系统)、烧蚀方法(多通道)和工艺参数优化(功率、速度、频率……)。(iii)需要先进的表征技术,以确保符合所需的质量标准,如3D轮廓仪,FIB横截面,SEM控制,AOI和3点模具强度。意法半导体将这种质量驱动的理念应用到所有BE制造工厂的大批量生产环境中。超快激光波长或用等离子体切割取代机械切割等新兴技术将进一步增强越来越脆弱的晶圆FE技术的稳健性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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