Plasma Dicing of Wafers for Reduced Total Cost of Ownership and Increased Quality

J. Weber, Shogo Okita
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Abstract

It could be argued that the defining feature of the Electronics Industry is the ability to miniaturize. Every person with a passing interest in electronics has heard of Moore’s Law: the processing power of affordable CPUs - or the number of transistors on a chip - will roughly double every two years. It is credit to both Gordon Moore’s foresight, and the technical and engineering teams around the world who continue to innovate, that the ‘Law’ is still even being discussed today. Part of the reason for chip size reduction lies in the shrinking of technology nodes (process geometries). Currently the smallest node that is being manufactured in mass volume is 7nm, and even smaller sizes are under development in the industry. The increase in processing power and speed and the miniaturization and integration of electronic functions that continue to result from such technological advances lie at the heart of the pervasiveness of electronics in our everyday lives: the smart phones that we rely on; the uptake of artificial intelligence in smart homes and cities; driverless vehicles; remote medical home diagnostics - there is not one aspect of life that electronic products and systems have not penetrated. But for this to continue, it is not only in the area of photolithographic processing that technology needs to keep innovating. Once a wafer has been created it must be singulated into individual dies, and as dies are becoming smaller and thinner, many products are facing difficulties caused by the singulation or dicing process. New challenges include: increasing material loss due to the width of the dicing street; mechanical damage such as chipping; and increasing processing time.Panasonic has developed a plasma dicing process which addresses these issues and in certain circumstances can replace mechanical dicing. Advantages of plasma dicing are:i.Damage-free / Chipping-free processii.Increased chip yield per waferiii.Water-free processiv.Flexible chip shapev.Fast etching speedvi.Total Dicing Process FlowThe throughput of a plasma chamber depends mainly on wafer thickness and wafer material, and is quite independent from wafer size or chip size. By using plasma dicing, the throughput can be more than 4 or 5 wafers per hour. Such throughput cannot be achieved by any line-by-line dicing method when small chips are required. Significant cost savings can be expected.The combination of higher throughput and increased chip yield per wafer lead to an overall reduced total cost of ownership, and the damage-free / chipping-free nature of plasma dicing leads to an increase of chip-strength and overall quality.
等离子切割晶圆片,降低总拥有成本,提高质量
可以说,电子工业的决定性特征是小型化的能力。每个对电子学稍有兴趣的人都听说过摩尔定律:可负担得起的cpu的处理能力——或者说芯片上晶体管的数量——大约每两年翻一番。这要归功于戈登·摩尔的远见卓识,以及世界各地不断创新的技术和工程团队,这条“定律”直到今天仍在被讨论。芯片尺寸减小的部分原因在于技术节点(工艺几何形状)的缩小。目前量产的最小节点是7nm,更小的尺寸正在开发中。技术进步带来的处理能力和速度的提高,以及电子功能的小型化和集成化,是我们日常生活中无处不在的电子产品的核心:我们依赖的智能手机;人工智能在智能家居和城市中的应用;无人驾驶车辆;远程家庭医疗诊断——电子产品和系统没有渗透到生活的方方面面。但要让这一切继续下去,不仅是在光刻处理领域,技术需要不断创新。一旦晶圆被制造出来,它就必须被分割成单独的模具,随着模具变得越来越小,越来越薄,许多产品都面临着由分割或分割过程引起的困难。新的挑战包括:由于掷骰子街的宽度增加了材料的损失;机械损伤,如碎裂;并增加处理时间。松下已经开发了一种等离子切割工艺,解决了这些问题,在某些情况下可以取代机械切割。等离子切割的优点是:我。免受伤害/ Chipping-free processii。提高每晶圆片的晶片产量。水的processiv。灵活的芯片形状。刻蚀速度快。等离子腔的吞吐量主要取决于晶圆厚度和晶圆材料,而与晶圆尺寸或芯片尺寸无关。通过使用等离子切割,每小时的吞吐量可超过4或5片晶圆。当需要小芯片时,这种吞吐量无法通过任何逐行切割方法实现。可以预期显著的成本节约。更高的吞吐量和每片晶圆芯片产量的增加导致总体拥有成本的降低,而等离子切割的无损伤/无芯片的性质导致芯片强度和整体质量的提高。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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