A Framework to Assess the Security of Advanced Integrated Circuit (IC) Packaging

Abstract

Packaging reliability has been discussed widely in both industry and academia. However, packaging security assessment is barely addressed in such communities. Adversarial changes in packaging parameters by a malicious manufacturer can result in undetected features, which can cause chip failure. Due to globalization and complexity of the microelectronics supply chain, such alterations can be easily implemented. A dishonest manufacturer can intentionally exploit packaging principles thus creating vulnerabilities in the chip nearly undetectable by the regular inspection process. This can cause severe problems in both short term and long term uses of the chip. Both cases are directly related to changes in packaging materials, namely the epoxy modeling compound, substrate material, and connection material. These hostile changes are even more difficult to detect post-manufacturing, as is the case for the end-users performing their own analysis on such chips. This is not only because the existing material characterization methods are destructive and time-consuming, but there are numerous unpredictable ways to maliciously change packaging property. In this paper, we will first study and analyze such vulnerabilities in advanced integrated circuit (IC) packaging and introduce the first ever taxonomy of vulnerabilities to the community to the best of our knowledge. To address the discussed shortfalls in packaging security assessment, this paper will also outline the requirements for new detection techniques necessary to address the packaging security before installation. These methods are especially useful in critical applications such as space, military, hospitals, power plants, etc.