发布求助
文献互助 智能选刊 最新文献

2015 IEEE Custom Integrated Circuits Conference (CICC)最新文献

筛选
英文 中文
A 0.622–10Gb/s inductorless adaptive linear equalizer with spectral tracking for data rate adaptation in 0.13-μm CMOS 基于光谱跟踪的0.13 μm CMOS数据速率自适应0.622-10Gb /s无电感线性均衡器
2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338375
S. Ray, M. Hella
{"title":"A 0.622–10Gb/s inductorless adaptive linear equalizer with spectral tracking for data rate adaptation in 0.13-μm CMOS","authors":"S. Ray, M. Hella","doi":"10.1109/CICC.2015.7338375","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338375","url":null,"abstract":"This paper presents an adaptive equalizer based on dual-loop balancing technique and a third order nested feedback equalizing filter to achieve data rate up to 10Gb/s without using inductors. A spectral balancing circuit adjusts the equalizer boost, while a second servo loop automatically tracks the data rate using self-calibration and re-tunes the filters for optimal equalization. Third order nested feedback is introduced in the equalizing filters to compensate for ~15dB channel loss for a highest data rate of 10Gb/s. Implemented in IBM 0.13-μm CMOS technology, the equalizer maintains an eye opening of 0.26, 0.44 and 0.5UI with BER<;10-12 for 5 Gb/s, 8.5Gb/s and 10Gb/s PRBS31 inputs, respectively. The chip dissipates 130 mW from a 1.2V power supply, while occupying an active area of 0.34 mm2.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"4 3 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78351761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A configurable 5.9 μW analog front-end for biosignal acquisition 一个可配置的5.9 μW模拟前端用于生物信号采集
2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338491
Tan Yang, Junjie Lu, M. S. Jahan, Kelly Griffin, Jeremy Langford, J. Holleman
{"title":"A configurable 5.9 μW analog front-end for biosignal acquisition","authors":"Tan Yang, Junjie Lu, M. S. Jahan, Kelly Griffin, Jeremy Langford, J. Holleman","doi":"10.1109/CICC.2015.7338491","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338491","url":null,"abstract":"This paper presents a configurable analog front-end (AFE) for the recordings of a variety of biopotential signals, including electromyography (EMG), electrocardiogram (ECG), electroencephalogram (EEG), action potential (AP) signals, etc. The first stage of the AFE employs a chopper-stabilized current-reuse complementary input (CRCI) telescopic-cascode amplifier to achieve high noise-power efficiency and suppress 1/f noise. A tunable impedance-boosting loop (IBL) is utilized, which is robust to process variation and parasitic capacitance and increases the input impedance from 4.3 MΩ to 102 MΩ. The proposed AFE is fabricated in a 0.13 μm CMOS process. The AFE has a mid-band gain from 45.2-71 dB. The low-pass corner is tunable in the range of 70-400 Hz and 1.2-7 kHz. When configured for EEG recordings (0.7-100 Hz), the AFE draws 5.4 μW from a 1.2 V supply while exhibiting input-referred noise of 0.45 μVrms, corresponding to a noise efficiency factor (NEF) of 3.7. When configured for AP recordings (0.7 Hz-7 kHz), the AFE consumes 5.9 μW with input referred noise of 2.93 μVrms and a NEF of 3.0.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"35 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79002260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Fast-transient asynchronous digital LDO with load regulation enhancement by soft multi-step switching and adaptive timing techniques in 65-nm CMOS 基于软多步开关和自适应时序技术的65nm CMOS负载调节增强快速瞬态异步数字LDO
2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338389
Fan Yang, P. Mok
{"title":"Fast-transient asynchronous digital LDO with load regulation enhancement by soft multi-step switching and adaptive timing techniques in 65-nm CMOS","authors":"Fan Yang, P. Mok","doi":"10.1109/CICC.2015.7338389","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338389","url":null,"abstract":"A digital low drop-out regulator (DLDO) load regulation enhancement technique which includes soft multi-step switching and adaptive timing is presented in this paper. As multi-step switching is widely used to balance the speed and resolution, a power-efficient method to improve the poor resolution during the switching between coarse- and finegrained regulations is in demand. The proposed technique, especially targeting at eliminating the undesired ripple voltage during multi-step switching, is implemented in a 65-nm asynchronous DLDO. This DLDO operates at an input voltage of 0.6V to 1V, and delivers a maximum of 500mA current with a 50mV drop-out voltage. In addition to responding to a nanoseconds' 500mA load current step and a 50mV per 10ns reference voltage change, an enhanced load regulation of 0.15mV/mA is achieved by adopting the proposed techniques.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"17 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79128881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
A 201 mV/pH, 375 fps and 512×576 CMOS ISFET sensor in 65nm CMOS technology 201mv /pH, 375 fps和512×576 CMOS ISFET传感器，采用65nm CMOS技术
2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338427
Yu Jiang, Xu Liu, Xiwei Huang, Jing Guo, Mei Yan, Hao Yu, Jui-Cheng Huang, K. Hsieh, Tung-Tsun Chen
{"title":"A 201 mV/pH, 375 fps and 512×576 CMOS ISFET sensor in 65nm CMOS technology","authors":"Yu Jiang, Xu Liu, Xiwei Huang, Jing Guo, Mei Yan, Hao Yu, Jui-Cheng Huang, K. Hsieh, Tung-Tsun Chen","doi":"10.1109/CICC.2015.7338427","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338427","url":null,"abstract":"This paper presents a high-gain and large-scale CMOS ion-sensitive field effect transistor (ISFET) sensor. The high-gain readout is achieved by a novel pH-to-Time-to-Voltage conversion (pH-TVC), which can greatly increase pixel density (small pixel size) with a high sensitivity. The proposed pH sensor consists of 512×576 pixel array with 3.9um×3.9um chemical sensing area, and is integrated with column-paralleled 10-bit single-slope ADCs to speed up data readout. It is fabricated in traditional TSMC 65nm process with 201mV/pH sensitivity and 375 fps readout speed, targeted for DNA sequencing.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"1 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84806768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A soft-error hardened process portable embedded microprocessor 一种软误差强化过程便携式嵌入式微处理器
2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338366
V. Vashishtha, L. Clark, S. Chellappa, Anudeep R. Gogulamudi, A. Gujja, Chad Farnsworth
{"title":"A soft-error hardened process portable embedded microprocessor","authors":"V. Vashishtha, L. Clark, S. Chellappa, Anudeep R. Gogulamudi, A. Gujja, Chad Farnsworth","doi":"10.1109/CICC.2015.7338366","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338366","url":null,"abstract":"An embedded microprocessor core designed to have high soft-error immunity is presented. The design achieves hardness via architectural, micro-architectural, and circuit techniques. The basis of the machine is a dual-redundant speculative pipeline that detects mismatches at their commission to architectural state. Added instructions allow software controlled recovery and restart of upset instructions. Key architectural state is stored in triple-mode redundant, self-correcting logic. Special automated place and route flows afford robustness against multiple node charge collection. Full clock gating allows low power, while redundant clocks mitigate clock upset induced errors. Register file based caches allow near-threshold low voltage operation. The design is implemented on a commercial 90-nm bulk CMOS process. Silicon results, including error correction examples, are presented.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"79 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84119642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A mixed-domain modeling method for RF systems 射频系统的混合域建模方法
2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338433
Zhimiao Chen, Zhixing Liu, Lei Liao, R. Wunderlich, S. Heinen
{"title":"A mixed-domain modeling method for RF systems","authors":"Zhimiao Chen, Zhixing Liu, Lei Liao, R. Wunderlich, S. Heinen","doi":"10.1109/CICC.2015.7338433","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338433","url":null,"abstract":"This paper introduces a mixed domain event-driven modeling method for RF systems. The circuit behaviors are modeled in time/frequency domain adaptively combining with the equivalent baseband representation of each spectral component. Comparing to traditional baseband modeling methods or harmonic balance simulation techniques, this mixed domain method loose the requirements of relations among carrier frequencies of spectral components, and therefore can be widely used in mixed-signal circuit modeling. Furthermore, this method brings in a great simulation speed up over the simulation in passband signal abstraction, while the modeling accuracy can be guaranteed to meet the requirements of functional verifications.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"20 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84400545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Design of PVT tolerant inverter based circuits for low supply voltages 低电源电压容限PVT逆变电路的设计
2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338424
R. Harjani, Rakesh Kumar Palani
{"title":"Design of PVT tolerant inverter based circuits for low supply voltages","authors":"R. Harjani, Rakesh Kumar Palani","doi":"10.1109/CICC.2015.7338424","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338424","url":null,"abstract":"The design of differential pair based OTAs is becoming increasingly difficult in finer geometries due to lower supply voltages. Inverter based designs have proven to have better transconductance efficiency, higher swing and better linearity but have degraded CMRR, worse PSRR and limited PVT tolerance. In this tutorial, we discuss traditional amplifiers and why inverter based amplifiers are better suited for lower supplies. We then describe the design procedure for inverter based OTA designs with an emphasis on improving their performance, including PVT tolerance, CMRR and PSRR. In particular, we introduce new biasing techniques for inverters to improve their PVT tolerance. We finally validate our designs using measurement results from a number of fabricated designs.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"25 1","pages":"1-8"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86514013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Session 4 — Frequency and phase generation techniques 第四部分-频率和相位生成技术
2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338464
F. Dai, S. Sankaran
{"title":"Session 4 — Frequency and phase generation techniques","authors":"F. Dai, S. Sankaran","doi":"10.1109/CICC.2015.7338464","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338464","url":null,"abstract":"This session presents techniques for frequency locking and schemes for phase generation with full 2π coverage at RF/mm-wave frequencies.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"18 1","pages":"1-1"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86614593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A single-inductor 7+7 ratio reconfigurable resonant switched-capacitor DC-DC converter with 0.1-to-1.5V output voltage range 单电感7+7比例可重构谐振开关电容DC-DC变换器，输出电压范围为0.1至1.5 v
2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338480
Loai G. Salem, P. Mercier
{"title":"A single-inductor 7+7 ratio reconfigurable resonant switched-capacitor DC-DC converter with 0.1-to-1.5V output voltage range","authors":"Loai G. Salem, P. Mercier","doi":"10.1109/CICC.2015.7338480","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338480","url":null,"abstract":"This paper demonstrates the first 7-ratio resonant switched capacitor (SC) converter using only a single inductor, realizing the widest resonant operating range reported in CMOS. A frequency-scaled gear train SC topology is introduced that enables soft-charging of all flying capacitors through one inductor at any arbitrary binary ratio by eliminating the inter-stage decoupling required in prior-art. Gear ratio modulation is proposed to control the resonance Q-factor, and hence the regulator can be gracefully transitioned from a resonant converter to a fully-capacitive SC, enabling > 24,000x output current range. For the same footprint, the converter achieves up to 14.4% and 12% efficiency improvements over co-fabricated SC and 3-level buck converters, respectively, while operating with a peak efficiency of 73.3% and current density of 0.14 A/mm2 in 0.18 μm bulk.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"30 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80547273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A novel low cost, high performance and reliable silicon interposer 一种新型低成本、高性能、可靠的硅中间体
2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338400
F. Yazdani
{"title":"A novel low cost, high performance and reliable silicon interposer","authors":"F. Yazdani","doi":"10.1109/CICC.2015.7338400","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338400","url":null,"abstract":"Silicon interposer has emerged as a substrate of choice for integrating fine pitch, high density devices. Conventional packaging of 2.5D/3D devices involves multiple level of assemblies. Normally, 2.5D/3D devices are first assembled on thinned silicon interposer with aspect ratio of 10:100 followed by second level assembly on a multi-layer organic build-up substrate. In this study we introduce direct assembly of silicon interposer on PCB, resulting in reduced cost and increased performance for 2.5D/3D applications as well as wafer-level fan-out applications. We investigate effect of under-fill on solder joint reliability during direct assembly of silicon interposer on PCB. A 10×10mm2 interposer test vehicle was designed and fabricated on 310um thick rigid silicon substrate. BGA of side of the interposer was bumped with eutectic solder balls through a reflow process. Interposer was then assembled on a 50×50mm2 FR-4 PCB through a reflow process. We present cost analysis, design flow, and direct assembly of rigid silicon interposer on PCB. Effect of under-fill on the solder joint reliability is demonstrated using CSAM images during temperature cycles at 250, 500, 750 and 1000 intervals. It is shown that all samples successfully passed the temperature cycle stress test.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"66 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73572647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信