2015 IEEE Custom Integrated Circuits Conference (CICC)最新文献_第5页

A 5.4-mW 4-Gb/s 5-band QPSK transceiver for frequency-division multiplexing memory interface 一种5.4 mw 4gb /s 5波段QPSK收发器，用于频分复用存储接口

2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338373

Wei-Han Cho, Yilei Li, Yanghyo Kim, Po-Tsang Huang, Yuan Du, S. Lee, Mau-Chung Frank Chang

引用次数: 26

A system-verilog behavioral model for PLLs for pre-silicon validation and top-down design methodology 用于预硅验证和自顶向下设计方法的锁相环的系统verilog行为模型

2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338432

Amr Lotfy, Syed Feruz Syed Farooq, Qi Wang, Soner Yaldiz, P. Mosalikanti, N. Kurd

引用次数: 9

ADC trends and impact on SAR ADC architecture and analysis ADC趋势及其对SAR ADC架构和分析的影响

2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338380

Jeffrey Fredenburg, M. Flynn

引用次数: 8

Materials challenges for III-V/Si co-integrated CMOS III-V/Si协积CMOS的材料挑战

2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338398

D. Sadana, C. Cheng, B. Wacaser, W. Spratt, K. Shiu, S. Bedell

{"title":"Materials challenges for III-V/Si co-integrated CMOS","authors":"D. Sadana, C. Cheng, B. Wacaser, W. Spratt, K. Shiu, S. Bedell","doi":"10.1109/CICC.2015.7338398","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338398","url":null,"abstract":"This review focuses on material challenges associated with III-V co-integration with Si for future CMOS. There is a huge volume of literature on this topic as implementation of III-V monolithic integration with Si has been the holy grail for last four decades; targeting a wide range of applications including RF devices, LEDs, lasers, photo-detectors and the like. The key drivers have been the cost reduction, scalability with Si wafer diameter, and accessibility to highly scaled integrated circuits next to III-V devices. With the current focus on CMOS the pace of progress on monolithic integration has accelerated by leaps and bounds partly because of its vast impact on CMOS scaling, and partly due to the aggressive CMOS roadmap requirements. The discussion below concentrates on In0.53Ga0.47As channel which is the dominant III-V material being pursued for future technology. Despite the narrow focus, fundamental and engineering challenges posed by this material encompass a broad range of material topics including epitaxial growth, crystallographic defects and their dynamics during growth and subsequent processing, clever device architecture to alleviate adverse impact of defects on device leakage, and innovative engineering for material improvement.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"22 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73180986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 2.2 GS/s 188mW spectrometer processor in 65nm CMOS for supporting low-power THz planetary instruments 一个2.2 GS/s 188mW的65纳米CMOS光谱仪处理器，支持低功耗太赫兹行星仪器

2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338367

F. Hsiao, A. Tang, Y. Kim, B. Drouin, G. Chattopadhyay, Mau-Chung Frank Chang

引用次数: 18

A 275 Gbps AES encryption accelerator using ROM-based S-boxes in 65nm 采用基于rom的s -box的275 Gbps AES加密加速器

2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338448

B. Erbagci, N. E. C. Akkaya, Craig Teegarden, K. Mai

引用次数: 10

A linear transconductance amplifier with differential-mode bandwidth extension and common-mode compensation 一种具有差模带宽扩展和共模补偿的线性跨导放大器

2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338443

Derui Kong, Sang Min Lee, S. M. Taleie, M. J. McGowan, Dongwon Seo

引用次数: 1

Methods for finding globally maximum-efficiency impedance matching networks with lossy passives 具有损耗无源的全局最大效率阻抗匹配网络的求解方法

2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338434

C. R. Chappidi, K. Sengupta

引用次数: 9

An on-chip stochastic sigma-tracking eye-opening monitor for BER-optimal adaptive equalization 一种用于ber最优自适应均衡的片上随机sigma跟踪大眼监视器

2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338374

Hyosup Won, Kwangseok Han, Sangeun Lee, Jinho Park, Hyeon-Min Bae

引用次数: 2

Dynamic and leakage power reduction of ASICs using configurable threshold logic gates 采用可配置阈值逻辑门降低asic的动态和泄漏功率

2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338369

Jinghua Yang, Joseph Davis, Niranjan S. Kulkarni, Jae-sun Seo, S. Vrudhula

{"title":"Dynamic and leakage power reduction of ASICs using configurable threshold logic gates","authors":"Jinghua Yang, Joseph Davis, Niranjan S. Kulkarni, Jae-sun Seo, S. Vrudhula","doi":"10.1109/CICC.2015.7338369","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338369","url":null,"abstract":"This article demonstrates an unconventional approach to computing logic functions for use in ASICs, and a fully automated approach to technology mapping for standard cell ASICs using the new cells. The approach results in a significant reduction in power, leakage, area and wire-length, without sacrificing performance of the design. At the heart of this approach is a configurable threshold logic gate. Using a standard cell library of such gates, a new technology mapping algorithm is applied to automatically transform a given netlist into one with an optimal mixture of conventional logic gates and threshold gates. The mapping algorithm is based on logic decomposition of Boolean functions into specific threshold functions. This approach was used to fabricate a 32-bit signed 2-stage Wallace-Tree multiplier in a 65-nm LP technology. Simulation and chip measurement results of the multiplier show a 33% improvement in dynamic power at 30% switching activity, 24% lower core area, 45% lower wire-length and 50% lower leakage without any performance degradation, compared to a functionally equivalent, conventional standard cell implementation. Similar results are shown for a FIR filter, a 32-bit MIPS, a 128-bit AES encryption circuit and a floating-point multiplier.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"6 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88807993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6