A system-verilog behavioral model for PLLs for pre-silicon validation and top-down design methodology

This paper presents a System-Verilog behavioral model for charge-pump PLLs based on piece-wise constant (PWC) real number modeling and table lookup. The proposed model exploits the sampled nature of the PLL where most of its analog behavior takes effect during the phase detection, and remains almost constant during the rest of the reference cycle. The PLL model simulation run time takes only 1 second, which makes it a perfect fit for pre-silicon digital validation as well as top-down design methodology. Compared to transistor-level Spice simulations, the proposed model shows a correlation of more than 97% for the PLL locking behavior, jitter, and phase noise. The PLL model is used to exercise critical features like spread-spectrum clocking (SSC) and adaptive frequency system (AFS). In addition, the model was integrated in a pre-silicon validation environment and enabled catching design bugs.