具有超紧凑输出网络的CMOS高线性双带混合模式极性功率放大器

2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI:10.1109/CICC.2015.7338362

Jong Seok Park, Song Hu, Yanjie Wang, Hua Wang

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引用次数: 22

摘要

本文提出了一种高度线性双带混合模式极性功率放大器，完全集成在标准65nm块体CMOS工艺中。超紧凑的单变压器无源网络提供双频最佳负载-拉力阻抗匹配，并联功率组合和双均匀谐波抑制，无需任何可调谐元件或频段选择开关。混合模式架构利用数字和模拟技术抑制AM-AM和AM-PM失真，并实现高线性度。作为概念验证设计，双频混合模式极性功率放大器在65nm CMOS工艺中实现。在2.6/4.5GHz频段，峰值输出功率为+28.1dBm/+26.0dBm，漏极效率为40.7%/27.0%。以1MSym/s 256-QAM信号进行测量，在2.35/4.7GHz时，平均输出功率为+21.51dBm/+19.27dBm，有效值EVM为2.05%/1.03%。测量到的2.35GHz信号的二次谐波抑制为37.7dB。

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A highly linear dual-band mixed-mode polar power amplifier in CMOS with an ultra-compact output network

This paper presents a highly linear dual-band mixed-mode polar power amplifier fully integrated in a standard 65nm bulk CMOS process. An ultra-compact single-transformer passive network provides dual-band optimum load-pull impedance matching, parallel power combining, and double even-harmonic rejection without any tunable element or band selection switch. The mixed-mode architecture leverages both digital and analog techniques to suppress the AM-AM and AM-PM distortions and achieves high linearity. As a proof-of-concept design, the dual-band mixed-mode polar power amplifier is implemented in a 65nm CMOS process. We demonstrate the peak output power of +28.1dBm/+26.0dBm with the PA drain efficiency of 40.7%/27.0% at 2.6/4.5GHz. Measurement with 1MSym/s 256-QAM signal achieves rms EVM of 2.05%/1.03% with the average output power of +21.51dBm/+19.27dBm at 2.35/4.7GHz. The measured 2nd-harmonic rejection for the 2.35GHz signal is 37.7dB.

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2015 IEEE Custom Integrated Circuits Conference (CICC)

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