2015 IEEE Custom Integrated Circuits Conference (CICC)最新文献

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Two-step beat frequency quantizer based ADC with adaptive reference control for low swing bio-potential signals 基于两步拍频量化和自适应参考控制的ADC用于低摆幅生物电位信号
2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338382
Somnath Kundu, Bongjin Kim, C. Kim
{"title":"Two-step beat frequency quantizer based ADC with adaptive reference control for low swing bio-potential signals","authors":"Somnath Kundu, Bongjin Kim, C. Kim","doi":"10.1109/CICC.2015.7338382","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338382","url":null,"abstract":"A two-step fully digital beat frequency quantizer based continuous time ADC is demonstrated in a 65nm test chip to achieve high resolution (6-7 ENOB) for direct conversion of low swing (<;10mV) bio-potential signals. The resolution of ADC can be adaptively controlled depending on the input signal swing. A triple-sampling technique generates a synchronous ADC output from an asynchronous beat frequency quantizer. The proposed two-step ADC achieves a 44.5dB SNDR which is 5.6dB higher than the previously proposed single step architecture for a 10mVpp, 300Hz differential input signal.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"59 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90872447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Session 9 — Advanced simulation techniques 第九部分-高级模拟技术
2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338467
C. McAndrew, L. Nagel
{"title":"Session 9 — Advanced simulation techniques","authors":"C. McAndrew, L. Nagel","doi":"10.1109/CICC.2015.7338467","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338467","url":null,"abstract":"As integrated circuits continue to increase in complexity and devices continue to decrease in size, more sophisticated modeling and simulation techniques are necessary to support designers. This session presents four papers describing a new modeling framework, new behavioral modeling techniques, and a new method of realizing impedance matching networks with lossy passive elements.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"32 1","pages":"1-1"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89515868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 110nA quiescent current buck converter with zero-power supply monitor and near-constant output ripple 一种110nA静态电流降压变换器,具有零电源监控和近恒定输出纹波
2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338393
Danzhu Lu, Suyi Yao, Bin Shao
{"title":"A 110nA quiescent current buck converter with zero-power supply monitor and near-constant output ripple","authors":"Danzhu Lu, Suyi Yao, Bin Shao","doi":"10.1109/CICC.2015.7338393","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338393","url":null,"abstract":"A 110nA quiescent current (IQ) buck converter for ultra-low power application is presented. A novel zero IQ pull-down structure, which consists in native NMOS and PJEF, is proposed to achieve zero-power supply monitor and save the total IQ. Implemented in 0.35um CMOS process, the converter realizes 78% efficiency in 1uA load and over 90% for load range from 5uA to 100mA. With adaptive-bias hysteresis comparator according to the load condition, near-constant output ripple is achieved in full load range without any efficiency deterioration.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"85 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77600048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 130nm canary SRAM for SRAM dynamic write VMIN tracking across voltage, frequency, and temperature variations 一个130nm金丝雀SRAM,用于SRAM动态写入VMIN跟踪跨电压,频率和温度变化
2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338495
A. Banerjee, J. Breiholz, B. Calhoun
{"title":"A 130nm canary SRAM for SRAM dynamic write VMIN tracking across voltage, frequency, and temperature variations","authors":"A. Banerjee, J. Breiholz, B. Calhoun","doi":"10.1109/CICC.2015.7338495","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338495","url":null,"abstract":"With device scaling in bulk technologies, process variation increases and SRAM VMIN scaling faces a bottleneck. Using peripheral assist techniques, we can lower the VMIN at the cost of energy and area. However, the SRAM VMIN is highly dependent on voltage, temperature, and operating frequency fluctuations, which are hard to determine in real time. Prior work shows theoretically that canary SRAMs using reverse assist can track SRAM dynamic write VMIN. In this paper, we show the first silicon results of a working 512b canary SRAM using bitline and wordline type reverse assists in a 130nm bulk technology. It has distinct canary failure trends across voltage, frequency, and temperature variations to track an 8Kb SRAM's dynamic write VMIN.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"18 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91528559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A configurable 5.9 μW analog front-end for biosignal acquisition 一个可配置的5.9 μW模拟前端用于生物信号采集
2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338491
Tan Yang, Junjie Lu, M. S. Jahan, Kelly Griffin, Jeremy Langford, J. Holleman
{"title":"A configurable 5.9 μW analog front-end for biosignal acquisition","authors":"Tan Yang, Junjie Lu, M. S. Jahan, Kelly Griffin, Jeremy Langford, J. Holleman","doi":"10.1109/CICC.2015.7338491","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338491","url":null,"abstract":"This paper presents a configurable analog front-end (AFE) for the recordings of a variety of biopotential signals, including electromyography (EMG), electrocardiogram (ECG), electroencephalogram (EEG), action potential (AP) signals, etc. The first stage of the AFE employs a chopper-stabilized current-reuse complementary input (CRCI) telescopic-cascode amplifier to achieve high noise-power efficiency and suppress 1/f noise. A tunable impedance-boosting loop (IBL) is utilized, which is robust to process variation and parasitic capacitance and increases the input impedance from 4.3 MΩ to 102 MΩ. The proposed AFE is fabricated in a 0.13 μm CMOS process. The AFE has a mid-band gain from 45.2-71 dB. The low-pass corner is tunable in the range of 70-400 Hz and 1.2-7 kHz. When configured for EEG recordings (0.7-100 Hz), the AFE draws 5.4 μW from a 1.2 V supply while exhibiting input-referred noise of 0.45 μVrms, corresponding to a noise efficiency factor (NEF) of 3.7. When configured for AP recordings (0.7 Hz-7 kHz), the AFE consumes 5.9 μW with input referred noise of 2.93 μVrms and a NEF of 3.0.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"35 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79002260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A technology-agnostic MTJ SPICE model with user-defined dimensions for STT-MRAM scalability studies 用于STT-MRAM可扩展性研究的具有用户定义维度的技术不可知MTJ SPICE模型
2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338407
Jongyeon Kim, An Chen, B. Behin-Aein, Saurabh Kumar, Jianping Wang, C. Kim
{"title":"A technology-agnostic MTJ SPICE model with user-defined dimensions for STT-MRAM scalability studies","authors":"Jongyeon Kim, An Chen, B. Behin-Aein, Saurabh Kumar, Jianping Wang, C. Kim","doi":"10.1109/CICC.2015.7338407","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338407","url":null,"abstract":"The development of a scalable and user-friendly SPICE model is a key aspect of exploring the potential of spin-transfer torque MRAM (STT-MRAM). A self-contained magnetic tunnel junction (MTJ) SPICE model is proposed in this work which can reproduce realistic MTJ characteristics based on user-defined input parameters such as the free layer's length, width, and thickness. Using the propose model, scalability studies of both in-plane and perpendicular MTJs can be performed across different technology nodes with minimal effort, which differentiates this model from most previously reported models.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"6 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89385139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 71
Fast-transient asynchronous digital LDO with load regulation enhancement by soft multi-step switching and adaptive timing techniques in 65-nm CMOS 基于软多步开关和自适应时序技术的65nm CMOS负载调节增强快速瞬态异步数字LDO
2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338389
Fan Yang, P. Mok
{"title":"Fast-transient asynchronous digital LDO with load regulation enhancement by soft multi-step switching and adaptive timing techniques in 65-nm CMOS","authors":"Fan Yang, P. Mok","doi":"10.1109/CICC.2015.7338389","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338389","url":null,"abstract":"A digital low drop-out regulator (DLDO) load regulation enhancement technique which includes soft multi-step switching and adaptive timing is presented in this paper. As multi-step switching is widely used to balance the speed and resolution, a power-efficient method to improve the poor resolution during the switching between coarse- and finegrained regulations is in demand. The proposed technique, especially targeting at eliminating the undesired ripple voltage during multi-step switching, is implemented in a 65-nm asynchronous DLDO. This DLDO operates at an input voltage of 0.6V to 1V, and delivers a maximum of 500mA current with a 50mV drop-out voltage. In addition to responding to a nanoseconds' 500mA load current step and a 50mV per 10ns reference voltage change, an enhanced load regulation of 0.15mV/mA is achieved by adopting the proposed techniques.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"17 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79128881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
A 0.622–10Gb/s inductorless adaptive linear equalizer with spectral tracking for data rate adaptation in 0.13-μm CMOS 基于光谱跟踪的0.13 μm CMOS数据速率自适应0.622-10Gb /s无电感线性均衡器
2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338375
S. Ray, M. Hella
{"title":"A 0.622–10Gb/s inductorless adaptive linear equalizer with spectral tracking for data rate adaptation in 0.13-μm CMOS","authors":"S. Ray, M. Hella","doi":"10.1109/CICC.2015.7338375","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338375","url":null,"abstract":"This paper presents an adaptive equalizer based on dual-loop balancing technique and a third order nested feedback equalizing filter to achieve data rate up to 10Gb/s without using inductors. A spectral balancing circuit adjusts the equalizer boost, while a second servo loop automatically tracks the data rate using self-calibration and re-tunes the filters for optimal equalization. Third order nested feedback is introduced in the equalizing filters to compensate for ~15dB channel loss for a highest data rate of 10Gb/s. Implemented in IBM 0.13-μm CMOS technology, the equalizer maintains an eye opening of 0.26, 0.44 and 0.5UI with BER<;10-12 for 5 Gb/s, 8.5Gb/s and 10Gb/s PRBS31 inputs, respectively. The chip dissipates 130 mW from a 1.2V power supply, while occupying an active area of 0.34 mm2.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"4 3 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78351761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Symmetry breaking in the drain current of multi-finger transistors 多指晶体管漏极电流的对称性破缺
2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338408
N. Lu, Sungjae Lee, R. Wachnik
{"title":"Symmetry breaking in the drain current of multi-finger transistors","authors":"N. Lu, Sungjae Lee, R. Wachnik","doi":"10.1109/CICC.2015.7338408","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338408","url":null,"abstract":"The drain current of a multi-finger MOSFET is typically calculated as the product of that of a single-finger MOSFET and the number of fingers. Careful investigation of currents in different fingers of a multi-finger transistor in the presence of parasitic effects shows differences between the per-finger drain current of the multi-finger transistor and the drain current of a corresponding single-finger transistor. We show that each of the following factors alone causes the drain current in one or more fingers of a multi-finger transistor to be different from that in other fingers of the transistor and the per-finger drain current of the multi-finger transistor to be different from the drain current of a corresponding single-finger transistor: (a) the resistance of wires that connect multiple fingers together, (b) the contact resistance, (c) the diffusion resistance, and (d) self heating. Excluding all of the above factors, the uncorrelated variations among the sub-threshold drain currents of different finger cause the per-finger median sub-threshold drain current of the multi-finger transistor to be different from the median sub-threshold drain current of the single-finger transistor.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"43 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84082421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An injection locked PLL for power supply variation robustness using negative phase shift phenomenon of injection locked frequency divider 利用注入锁定分频器的负相移现象,实现电源变化鲁棒性的注入锁定锁相环
2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338404
Dongil Lee, Taeho Lee, Yong-Hun Kim, Young-Ju Kim, L. Kim
{"title":"An injection locked PLL for power supply variation robustness using negative phase shift phenomenon of injection locked frequency divider","authors":"Dongil Lee, Taeho Lee, Yong-Hun Kim, Young-Ju Kim, L. Kim","doi":"10.1109/CICC.2015.7338404","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338404","url":null,"abstract":"This paper presents a 2 GHz injection-locked PLL (ILPLL) with an injection-locked frequency divider (ILFD). Using a negative phase shift phenomenon of the ILFD, injection timing can be calibrated without a delay line. As a result, the proposed ILPLL achieves a simple background injection timing calibration for robustness of power supply variation. The test core has been fabricated in 65nm CMOS process consuming 3.74mW at 0.9V supply voltage.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"14 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91315382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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