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2015 IEEE Custom Integrated Circuits Conference (CICC)最新文献

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Two-step beat frequency quantizer based ADC with adaptive reference control for low swing bio-potential signals 基于两步拍频量化和自适应参考控制的ADC用于低摆幅生物电位信号
2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338382
Somnath Kundu, Bongjin Kim, C. Kim
{"title":"Two-step beat frequency quantizer based ADC with adaptive reference control for low swing bio-potential signals","authors":"Somnath Kundu, Bongjin Kim, C. Kim","doi":"10.1109/CICC.2015.7338382","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338382","url":null,"abstract":"A two-step fully digital beat frequency quantizer based continuous time ADC is demonstrated in a 65nm test chip to achieve high resolution (6-7 ENOB) for direct conversion of low swing (<;10mV) bio-potential signals. The resolution of ADC can be adaptively controlled depending on the input signal swing. A triple-sampling technique generates a synchronous ADC output from an asynchronous beat frequency quantizer. The proposed two-step ADC achieves a 44.5dB SNDR which is 5.6dB higher than the previously proposed single step architecture for a 10mVpp, 300Hz differential input signal.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"59 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90872447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Session 9 — Advanced simulation techniques 第九部分-高级模拟技术
2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338467
C. McAndrew, L. Nagel
{"title":"Session 9 — Advanced simulation techniques","authors":"C. McAndrew, L. Nagel","doi":"10.1109/CICC.2015.7338467","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338467","url":null,"abstract":"As integrated circuits continue to increase in complexity and devices continue to decrease in size, more sophisticated modeling and simulation techniques are necessary to support designers. This session presents four papers describing a new modeling framework, new behavioral modeling techniques, and a new method of realizing impedance matching networks with lossy passive elements.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"32 1","pages":"1-1"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89515868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 110nA quiescent current buck converter with zero-power supply monitor and near-constant output ripple 一种110nA静态电流降压变换器，具有零电源监控和近恒定输出纹波
2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338393
Danzhu Lu, Suyi Yao, Bin Shao
{"title":"A 110nA quiescent current buck converter with zero-power supply monitor and near-constant output ripple","authors":"Danzhu Lu, Suyi Yao, Bin Shao","doi":"10.1109/CICC.2015.7338393","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338393","url":null,"abstract":"A 110nA quiescent current (IQ) buck converter for ultra-low power application is presented. A novel zero IQ pull-down structure, which consists in native NMOS and PJEF, is proposed to achieve zero-power supply monitor and save the total IQ. Implemented in 0.35um CMOS process, the converter realizes 78% efficiency in 1uA load and over 90% for load range from 5uA to 100mA. With adaptive-bias hysteresis comparator according to the load condition, near-constant output ripple is achieved in full load range without any efficiency deterioration.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"85 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77600048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 130nm canary SRAM for SRAM dynamic write VMIN tracking across voltage, frequency, and temperature variations 一个130nm金丝雀SRAM，用于SRAM动态写入VMIN跟踪跨电压，频率和温度变化
2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338495
A. Banerjee, J. Breiholz, B. Calhoun
{"title":"A 130nm canary SRAM for SRAM dynamic write VMIN tracking across voltage, frequency, and temperature variations","authors":"A. Banerjee, J. Breiholz, B. Calhoun","doi":"10.1109/CICC.2015.7338495","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338495","url":null,"abstract":"With device scaling in bulk technologies, process variation increases and SRAM VMIN scaling faces a bottleneck. Using peripheral assist techniques, we can lower the VMIN at the cost of energy and area. However, the SRAM VMIN is highly dependent on voltage, temperature, and operating frequency fluctuations, which are hard to determine in real time. Prior work shows theoretically that canary SRAMs using reverse assist can track SRAM dynamic write VMIN. In this paper, we show the first silicon results of a working 512b canary SRAM using bitline and wordline type reverse assists in a 130nm bulk technology. It has distinct canary failure trends across voltage, frequency, and temperature variations to track an 8Kb SRAM's dynamic write VMIN.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"18 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91528559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A technology-agnostic MTJ SPICE model with user-defined dimensions for STT-MRAM scalability studies 用于STT-MRAM可扩展性研究的具有用户定义维度的技术不可知MTJ SPICE模型
2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338407
Jongyeon Kim, An Chen, B. Behin-Aein, Saurabh Kumar, Jianping Wang, C. Kim
{"title":"A technology-agnostic MTJ SPICE model with user-defined dimensions for STT-MRAM scalability studies","authors":"Jongyeon Kim, An Chen, B. Behin-Aein, Saurabh Kumar, Jianping Wang, C. Kim","doi":"10.1109/CICC.2015.7338407","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338407","url":null,"abstract":"The development of a scalable and user-friendly SPICE model is a key aspect of exploring the potential of spin-transfer torque MRAM (STT-MRAM). A self-contained magnetic tunnel junction (MTJ) SPICE model is proposed in this work which can reproduce realistic MTJ characteristics based on user-defined input parameters such as the free layer's length, width, and thickness. Using the propose model, scalability studies of both in-plane and perpendicular MTJs can be performed across different technology nodes with minimal effort, which differentiates this model from most previously reported models.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"6 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89385139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 71
Symmetry breaking in the drain current of multi-finger transistors 多指晶体管漏极电流的对称性破缺
2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338408
N. Lu, Sungjae Lee, R. Wachnik
{"title":"Symmetry breaking in the drain current of multi-finger transistors","authors":"N. Lu, Sungjae Lee, R. Wachnik","doi":"10.1109/CICC.2015.7338408","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338408","url":null,"abstract":"The drain current of a multi-finger MOSFET is typically calculated as the product of that of a single-finger MOSFET and the number of fingers. Careful investigation of currents in different fingers of a multi-finger transistor in the presence of parasitic effects shows differences between the per-finger drain current of the multi-finger transistor and the drain current of a corresponding single-finger transistor. We show that each of the following factors alone causes the drain current in one or more fingers of a multi-finger transistor to be different from that in other fingers of the transistor and the per-finger drain current of the multi-finger transistor to be different from the drain current of a corresponding single-finger transistor: (a) the resistance of wires that connect multiple fingers together, (b) the contact resistance, (c) the diffusion resistance, and (d) self heating. Excluding all of the above factors, the uncorrelated variations among the sub-threshold drain currents of different finger cause the per-finger median sub-threshold drain current of the multi-finger transistor to be different from the median sub-threshold drain current of the single-finger transistor.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"43 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84082421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 5GS/s 10b 76mW time-interleaved SAR ADC in 28nm CMOS 基于28nm CMOS的5GS/s 10b 76mW时间交错SAR ADC
2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338385
Jie Fang, S. Thirunakkarasu, Xuefeng Yu, F. Silva-Rivas, Kwang Young Kim, Chaoming Zhang, Frank W. Singor
{"title":"A 5GS/s 10b 76mW time-interleaved SAR ADC in 28nm CMOS","authors":"Jie Fang, S. Thirunakkarasu, Xuefeng Yu, F. Silva-Rivas, Kwang Young Kim, Chaoming Zhang, Frank W. Singor","doi":"10.1109/CICC.2015.7338385","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338385","url":null,"abstract":"This paper presents a 5GS/s 12-way 10b time-interleaved SAR ADC. Each SAR sub-ADC resolves 11b using reduced radix-2 with 1b redundancy, which tolerates decision errors arising from noise, reference settling error, etc. The top-plate sampling with merged capacitor switching algorithm is applied to achieve high switching efficiency, small area and less comparator noise. Several design techniques for sampling network, comparator and highspeed reference buffer are illustrated to achieve a high-efficient ADC. The scheme for the reference voltages optimizes the input of comparator to reduce decision errors during LSB conversion cycles. Gain and offset mismatches are corrected by a digital background calibration. Timing-skew mismatches are estimated offline, then calibrated by the programmable delay of the sampling clock. The ADC achieves 49dB SNR, 52dB THD and 42dB SNDR up to Nyquist frequency at 5GS/s, consumes 76mW from 1V supply, and occupies 0.57mm2 in 28nm CMOS technology.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"13 2 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86827037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A highly linear dual-band mixed-mode polar power amplifier in CMOS with an ultra-compact output network 具有超紧凑输出网络的CMOS高线性双带混合模式极性功率放大器
2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338362
Jong Seok Park, Song Hu, Yanjie Wang, Hua Wang
{"title":"A highly linear dual-band mixed-mode polar power amplifier in CMOS with an ultra-compact output network","authors":"Jong Seok Park, Song Hu, Yanjie Wang, Hua Wang","doi":"10.1109/CICC.2015.7338362","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338362","url":null,"abstract":"This paper presents a highly linear dual-band mixed-mode polar power amplifier fully integrated in a standard 65nm bulk CMOS process. An ultra-compact single-transformer passive network provides dual-band optimum load-pull impedance matching, parallel power combining, and double even-harmonic rejection without any tunable element or band selection switch. The mixed-mode architecture leverages both digital and analog techniques to suppress the AM-AM and AM-PM distortions and achieves high linearity. As a proof-of-concept design, the dual-band mixed-mode polar power amplifier is implemented in a 65nm CMOS process. We demonstrate the peak output power of +28.1dBm/+26.0dBm with the PA drain efficiency of 40.7%/27.0% at 2.6/4.5GHz. Measurement with 1MSym/s 256-QAM signal achieves rms EVM of 2.05%/1.03% with the average output power of +21.51dBm/+19.27dBm at 2.35/4.7GHz. The measured 2nd-harmonic rejection for the 2.35GHz signal is 37.7dB.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"8 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85572978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
Recent advances in Ga N MMIC technology Ga - N - MMIC技术的最新进展
2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338399
N. Kolias
{"title":"Recent advances in Ga N MMIC technology","authors":"N. Kolias","doi":"10.1109/CICC.2015.7338399","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338399","url":null,"abstract":"GaN MMIC technology is now in production and is revolutionizing microwave Radar and Communication systems. In this paper we present an overview of GaN MMIC technology, focusing on device characteristics, reliability, and high frequency performance. We also introduce emerging GaN technologies such as GaN-on-diamond and the heterogeneous integration of GaN with Silicon.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"12 6","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91475808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
An injection locked PLL for power supply variation robustness using negative phase shift phenomenon of injection locked frequency divider 利用注入锁定分频器的负相移现象，实现电源变化鲁棒性的注入锁定锁相环
2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338404
Dongil Lee, Taeho Lee, Yong-Hun Kim, Young-Ju Kim, L. Kim
{"title":"An injection locked PLL for power supply variation robustness using negative phase shift phenomenon of injection locked frequency divider","authors":"Dongil Lee, Taeho Lee, Yong-Hun Kim, Young-Ju Kim, L. Kim","doi":"10.1109/CICC.2015.7338404","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338404","url":null,"abstract":"This paper presents a 2 GHz injection-locked PLL (ILPLL) with an injection-locked frequency divider (ILFD). Using a negative phase shift phenomenon of the ILFD, injection timing can be calibrated without a delay line. As a result, the proposed ILPLL achieves a simple background injection timing calibration for robustness of power supply variation. The test core has been fabricated in 65nm CMOS process consuming 3.74mW at 0.9V supply voltage.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"14 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91315382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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