A 5GS/s 10b 76mW time-interleaved SAR ADC in 28nm CMOS

Abstract

This paper presents a 5GS/s 12-way 10b time-interleaved SAR ADC. Each SAR sub-ADC resolves 11b using reduced radix-2 with 1b redundancy, which tolerates decision errors arising from noise, reference settling error, etc. The top-plate sampling with merged capacitor switching algorithm is applied to achieve high switching efficiency, small area and less comparator noise. Several design techniques for sampling network, comparator and highspeed reference buffer are illustrated to achieve a high-efficient ADC. The scheme for the reference voltages optimizes the input of comparator to reduce decision errors during LSB conversion cycles. Gain and offset mismatches are corrected by a digital background calibration. Timing-skew mismatches are estimated offline, then calibrated by the programmable delay of the sampling clock. The ADC achieves 49dB SNR, 52dB THD and 42dB SNDR up to Nyquist frequency at 5GS/s, consumes 76mW from 1V supply, and occupies 0.57mm2 in 28nm CMOS technology.