2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)最新文献_第4页

Pipeline design in spintronic circuits 自旋电子电路中的管路设计

2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2014-07-08 DOI: 10.1145/2770287.2770314

N. Kani, A. Naeemi

引用次数: 3

A memristor-based TCAM (Ternary Content Addressable Memory) cell 基于忆阻器的TCAM(三元内容可寻址存储器)单元

2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2014-07-08 DOI: 10.1145/2770287.2770289

P. Junsangsri, F. Lombardi, Jie Han

引用次数: 22

Analog-to-stochastic converter using magnetic-tunnel junction devices 采用磁隧道结装置的模拟-随机变换器

2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2014-07-08 DOI: 10.1145/2770287.2770303

N. Onizawa, Daisaku Katagiri, W. Gross, T. Hanyu

引用次数: 21

STT-MRAM based low power synchronous non-volatile logic with timing demultiplexing 基于STT-MRAM的低功耗同步非易失性逻辑与定时解复用

2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2014-07-08 DOI: 10.1145/2770287.2770295

Kejie Huang, Rong Zhao, Y. Lian

{"title":"STT-MRAM based low power synchronous non-volatile logic with timing demultiplexing","authors":"Kejie Huang, Rong Zhao, Y. Lian","doi":"10.1145/2770287.2770295","DOIUrl":"https://doi.org/10.1145/2770287.2770295","url":null,"abstract":"The high power and long global interconnection delay are two of the major limits for further scaling down of the process nodes in the very large scale integrated (VLSI) systems. Therefore, new technologies and computer architectures are under focused development to reduce the power consumption and interconnection delay. Magnetic tunnel junction (MTJ) nanopillar with the advantages of non-volatility, fast switching speed, and high density promises new designs and architectures to significantly alleviate the power and delay issues. This paper presents new logic-in-memory designs of the basic logic gates based on MTJs, including INV, (N)AND, (N)OR and XOR. The MTJ sharing and timing demultiplexing techniques are used in the proposed non-volatile logic gates to greatly reduce the write power. The simulation results show that the write power of the proposed non-volatile logic gates is as low as 285fJ/bit. The basic logic gates can finish the read operation in less than 160ps with 4.35f J read energy. Moreover, the proposed non-volatile logic gates may be reconfigured after fabrication, which makes the designs more flexible and robust.","PeriodicalId":6519,"journal":{"name":"2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"41 1","pages":"31-36"},"PeriodicalIF":0.0,"publicationDate":"2014-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82290095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

Monte Carlo simulations of carbon nanotube networks for optoelectronic applications 光电应用中碳纳米管网络的蒙特卡罗模拟

2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2014-07-08 DOI: 10.1145/2770287.2770319

Miguel Diez-Garcia, A. Vincent, N. Izard, D. Querlioz

引用次数: 0

Floating-point unit design with nano-electro-mechanical (NEM) relays 带有纳米机电(NEM)继电器的浮点单元设计

2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2014-07-08 DOI: 10.1145/2770287.2770323

S. Dutta, V. Stojanović

{"title":"Floating-point unit design with nano-electro-mechanical (NEM) relays","authors":"S. Dutta, V. Stojanović","doi":"10.1145/2770287.2770323","DOIUrl":"https://doi.org/10.1145/2770287.2770323","url":null,"abstract":"Digital circuits made with nano-electro-mechanical (NEM) relays offer energy-efficiency benefits over CMOS since they have zero leakage power and can offer circuit level performance that competes with CMOS. In this paper we show how new relay circuit design techniques combined with those we already demonstrated on smaller relay blocks enable us to optimize the design of the most complex arithmetic unit, the floating-point unit (FPU). The energy, performance, and area trade-offs of FPU designs with NEM relays are examined and compared with those of state-of-the-art CMOS designs in an equivalent scaled process. Circuits that are critical path bottlenecks for the FPU specifically, most notably the leading zero detector (LZD) and leading zero anticipator (LZA), are optimized with new relay-tailored circuit techniques. These optimizations reduce the NEM relay FPU latency from 71 mechanical delays in an optimal-CMOS-style implementation to 16 mechanical delays in a generalized custom NEM relay implementation. In a 90 nm process node, the FPU designed with NEM relays is projected to achieve 15× lower energy per operation compared to the FPU designed with CMOS.","PeriodicalId":6519,"journal":{"name":"2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"300 1","pages":"145-150"},"PeriodicalIF":0.0,"publicationDate":"2014-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83086629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Volatile memristive devices as short-term memory in a neuromorphic learning architecture 易失性记忆装置在神经形态学习结构中的短期记忆作用

2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2014-07-08 DOI: 10.1145/2770287.2770313

Jens Bürger, C. Teuscher

引用次数: 9

A model for variation- and fault-tolerant digital logic using self-assembled nanowire architectures 使用自组装纳米线架构的变化和容错数字逻辑模型

2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2014-06-12 DOI: 10.1145/2770287.2770315

A. Goudarzi, Matthew R. Lakin, D. Stefanovic, C. Teuscher

{"title":"A model for variation- and fault-tolerant digital logic using self-assembled nanowire architectures","authors":"A. Goudarzi, Matthew R. Lakin, D. Stefanovic, C. Teuscher","doi":"10.1145/2770287.2770315","DOIUrl":"https://doi.org/10.1145/2770287.2770315","url":null,"abstract":"Reconfiguration has been used for both defect- and fault-tolerant nanoscale architectures with regular structure. Recent advances in self-assembled nanowires have opened doors to a new class of electronic devices with irregular structure. For such devices, reservoir computing has been shown to be a viable approach to implement computation. This approach exploits the dynamical properties of a system rather than specifics of its structure. Here, we extend a model of reservoir computing, called the echo state network, to reflect more realistic aspects of self-assembled nanowire networks. As a proof of concept, we use echo state networks to implement basic building blocks of digital computing: AND, OR, and XOR gates, and 2-bit adder and multiplier circuits. We show that the system can operate perfectly in the presence of variations five orders of magnitude higher than ITRS's 2005 target, 6%, and achieves success rates 6 times higher than related approaches at half the cost. We also describe an adaptive algorithm that can detect faults in the system and reconfigure it to resume perfect operational condition.","PeriodicalId":6519,"journal":{"name":"2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"136 1","pages":"116-121"},"PeriodicalIF":0.0,"publicationDate":"2014-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77363517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Design exploration of ultra-low power non-volatile memory based on topological insulator 基于拓扑绝缘体的超低功耗非易失性存储器设计探索

2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2012-07-04 DOI: 10.1145/2765491.2765498

Yuhao Wang, Hao Yu

引用次数: 4