2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)最新文献

Mosaic: A scheme of mapping non-volatile Boolean logic on memristor crossbar 镶嵌:一种将非易失性布尔逻辑映射到忆阻器横条上的方案

2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2016-07-18 DOI: 10.1145/2950067.2950088

Lei Xie

引用次数: 0

MECRO: A local processing computer architecture based on memristor crossbar 一种基于忆阻交叉棒的本地处理计算机体系结构

2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2016-07-18 DOI: 10.1145/2950067.2950099

Lei Xie, M. A. Haron

{"title":"MECRO: A local processing computer architecture based on memristor crossbar","authors":"Lei Xie, M. A. Haron","doi":"10.1145/2950067.2950099","DOIUrl":"https://doi.org/10.1145/2950067.2950099","url":null,"abstract":"As the need of data-intensive (or big data) applications is growing, the exascale system (i.e., capable of executing 1018 operations per second) is desired. However, it is challenging to scale von Neumann architecture to meet this need, due to its unavoidable data movement between processors and memories. To address such a challenge, this paper proposes a local-processing computer architecture (MECRO) based on memristor crossbar, which consists both microarchitecture and instruction set. Differing from von Neumann architecture, MECRO executes all operations locally in the memristor-based memory using stateful logic operations, where the same devices simultaneously serve as both logic and memory. In addition, this paper proposes a new multiplication arithmetic algorithm that is suitable for MECRO. n×n matrix multiplication is used as example of data-intensive applications. MECRO is verified with SPICE simulations in a small scale. Comparing with a von Neumann architecture consisting of p processors, the experiment shows that MECRO is able to improve the execution time in an order of O(n2/p), while using the similar memory (O(n3)).","PeriodicalId":6519,"journal":{"name":"2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"29 1","pages":"85-90"},"PeriodicalIF":0.0,"publicationDate":"2016-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80480737","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design and analysis of Racetrack memory based on magnetic domain wall motion in nanowires 基于纳米线磁畴壁运动的赛马场存储器设计与分析

2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2014-07-08 DOI: 10.1145/2770287.2770305

N. B. Romdhane, Weisheng Zhao, Yue Zhang, Jacques-Olivier Klein, Z. Wang, D. Ravelosona

引用次数: 15

Memristor content addressable memory 忆阻器内容可寻址存储器

2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2014-07-08 DOI: 10.1145/2770287.2770308

Wanlong Chen, X. Yang, Frank Z. Wang

引用次数: 9

A CMOS-memristive self-learning neural network for pattern classification applications 一种用于模式分类的cmos记忆自学习神经网络

2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2014-07-08 DOI: 10.1145/2770287.2770311

M. Payvand, Justin Rofeh, A. Sodhi, L. Theogarajan

引用次数: 21

Sneak paths effects in CBRAM memristive devices arrays for spiking neural networks 脉冲神经网络中CBRAM记忆器件阵列的潜行路径效应

2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2014-07-08 DOI: 10.1145/2770287.2770291

David Roclin, O. Bichler, C. Gamrat, Jacques-Olivier Klein

引用次数: 7

On the influence of synaptic weight states in a locally competitive algorithm for memristive hardware 忆阻硬件局部竞争算法中突触权态的影响

2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2014-07-08 DOI: 10.1145/2770287.2770292

Walt Woods, Jens Bürger, C. Teuscher

{"title":"On the influence of synaptic weight states in a locally competitive algorithm for memristive hardware","authors":"Walt Woods, Jens Bürger, C. Teuscher","doi":"10.1145/2770287.2770292","DOIUrl":"https://doi.org/10.1145/2770287.2770292","url":null,"abstract":"Memristors promise a means for very compact neu-romorphic nanoscale architectures that leverage in-situ learning algorithms. While traditional learning algorithms simulated in software commonly assume analog values for synaptic weights, actual physical memristors may have a finite set of achievable states during online learning. In this paper we simulate a learning algorithm with limitations on both the resolution of its weights and the means of switching between them to gain an appreciation for how these properties might affect classification performance. For our experiments we use the Locally Competitive Algorithm (LCA) by Rozell et al. in conjunction with the MNIST dataset. We investigate the effects of both linear and non-linear distributions of weight states, concluding that as long as the weights are roughly within a power law distribution close to linear the algorithm is still effective. Our results also show that the resolution required from a device depends on its transition function between states; for transitions akin to round to nearest, synaptic weights should have around 16 possible states (4-bit resolution) to obtain optimal results. We find that lowering the threshold required to change states or adding stochasticity to the system can reduce that requirement down to 4 states (2-bit resolution). The outcomes of our research are relevant for building neuromorphic hardware with state-of-the art memristive devices.","PeriodicalId":6519,"journal":{"name":"2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"38 1","pages":"19-24"},"PeriodicalIF":0.0,"publicationDate":"2014-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87068088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Hysteresis-free carbon nanotube field-effect transistors without passivation 无迟滞无钝化的碳纳米管场效应晶体管

2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2014-07-08 DOI: 10.1145/2770287.2770320

J. Tittmann, S. Hermann, S. Schulz, A. Pacheco-Sánchez, M. Claus, M. Schröter

引用次数: 4

On-chip supervised learning rule for ultra high density neural crossbar using memristor for synapse and neuron 基于记忆电阻器的超高密度神经交叉杆片上监督学习规则

2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2014-07-08 DOI: 10.1145/2770287.2770290

Djaafar Chabi, Zhaohao Wang, Weisheng Zhao, Jacques-Olivier Klein

{"title":"On-chip supervised learning rule for ultra high density neural crossbar using memristor for synapse and neuron","authors":"Djaafar Chabi, Zhaohao Wang, Weisheng Zhao, Jacques-Olivier Klein","doi":"10.1145/2770287.2770290","DOIUrl":"https://doi.org/10.1145/2770287.2770290","url":null,"abstract":"The memristor-based neural learning network is considered as one of the candidates for future computing systems thanks to its low power, high density and defect-tolerance. However, its application is still hindered by the limitations of huge neuron structure and complicated learning cell. In this paper, we present a memristor-based neural crossbar circuit to implement on-chip supervised learning rule. In our work, activation function of neuron is implemented with simple CMOS inverter to save area overhead. Importantly, we propose a compact learning cell with a crossbar latch consisting of two antiparallel oriented binary memristors. This scheme allows high density integration and could improve the reliability of learning circuit. We describe firstly the circuit architecture, memristor model and operation process of supervised learning rule. Afterwards we perform transient simulation with CMOS 40nm design kit to validate the function of proposed learning circuit. Analysis and evaluation demonstrate that our circuit show great potential in on-chip learning.","PeriodicalId":6519,"journal":{"name":"2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"41 1","pages":"7-12"},"PeriodicalIF":0.0,"publicationDate":"2014-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86835809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 19

Molecular transistor circuits: From device model to circuit simulation 分子晶体管电路:从器件模型到电路仿真

2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2014-07-08 DOI: 10.1145/2770287.2770318

A. Zahir, Syed Azhar Ali Zaidi, A. Pulimeno, M. Graziano, D. Demarchi, G. Masera, G. Piccinini

{"title":"Molecular transistor circuits: From device model to circuit simulation","authors":"A. Zahir, Syed Azhar Ali Zaidi, A. Pulimeno, M. Graziano, D. Demarchi, G. Masera, G. Piccinini","doi":"10.1145/2770287.2770318","DOIUrl":"https://doi.org/10.1145/2770287.2770318","url":null,"abstract":"Molecular devices have been proposed as an alternative solution for the design and fabrication of complex logic functions. In this paper a hybrid model of the molecular transistor (MT) is used to simulate different logic circuits. The model is based on the density function theory (DFT) combined with the Non Equilibrium Greens Function (NEGF) to find the transmission spectrum (TS) at equilibrium. The self-consistent method is used to calculate the I-V characteristics at nonequilibrium condition, considering the more realistic case of broadening of energy levels under the assumption of strong molecule electrode coupling. We have used a four terminal device with source, drain and two gate electrodes: one (backgate) used to increase the ION/IOFF ratio and the other as normal control gate. The very same device is contextualized in the case of a structure feasible with currently available technology and several technological parameters are used to explore the solution space. This ensemble has been described and simulated using VHDL-AMS and allowed the design of a library of logic cells e.g NAND, NOR, Inverter and Half Adder suitable for architecture design. Results are given on both the modeling level and the circuits functional performance. Our findings represent an important breakthrough in the state of the art 1) for the methodology and design flow used and 2) for the detailed understanding on the device analyzed and optimized with the point of view of the circuit designer.","PeriodicalId":6519,"journal":{"name":"2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"22 1","pages":"129-134"},"PeriodicalIF":0.0,"publicationDate":"2014-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75865062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15