2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)最新文献_第2页

NBTI aware IG-FinFET based SRAM design using adaptable trip-point sensing technique 基于自适应跳闸点传感技术的NBTI感知IG-FinFET SRAM设计

2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2014-07-08 DOI: 10.1145/2770287.2770316

N. Yadav, Shikha Jain, M. Pattanaik, G. K. Sharma

引用次数: 7

A low contact resistance graphene field effect transistor with single-layer-channel and multi-layer-contact 一种具有单层通道和多层触点的低接触电阻石墨烯场效应晶体管

2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2014-07-08 DOI: 10.1145/2770287.2770321

Honghui Sun, Liang Fang, Yao Wang, Yaqing Chi, Rulin Liu

{"title":"A low contact resistance graphene field effect transistor with single-layer-channel and multi-layer-contact","authors":"Honghui Sun, Liang Fang, Yao Wang, Yaqing Chi, Rulin Liu","doi":"10.1145/2770287.2770321","DOIUrl":"https://doi.org/10.1145/2770287.2770321","url":null,"abstract":"As of today, the semiconductor industry has been looking for possible alternative materials of silicon, since the physical limitation of silicon-based devices, i.e., planar CMOS devices for most of the scenarios, is approaching soon. Among all the novel materials arising from the horizon, graphene is considered to be a very promising alternative for its unique electrical properties. Although all kinds of prospective electrical properties it has(e.g., high mobility), there are barriers for Graphene-based Field Effect Transistors (G-FETs) to overcome, in order to find its way to the substitution of Silicon Metal Oxide Semiconducting Field Effect Transistors (Si-MOSFETs). One of the most important engineering barriers to be overwhelmed is the parasitic parameters, among which the parasitic resistance is considered to be one of the most critical roadblock. Contact resistance in G-FETs is relatively high compared to that of conventional Si-MOSFETs. In this paper, we present an experimental demonstration of a new method to reduce the contact resistance in back gate G-FETs. In the proposed device structure, the source/drain regions are fabricated using multilayer graphene (MLG), thus the top and edge contacts are formed between the MLG and metal electrodes, while the conducting channel is still formed by using single-layer graphene (SLG). Due to the high conductivity of MLG and relative low conductivity of SLG, the contact resistance is reduced while the controllability of channel conductivity is preserved.","PeriodicalId":6519,"journal":{"name":"2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"35 1","pages":"139-144"},"PeriodicalIF":0.0,"publicationDate":"2014-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84501394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Compression architecture for bit-write reduction in non-volatile memory technologies 非易失性存储器技术中减少位写入的压缩体系结构

2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2014-07-08 DOI: 10.1145/2770287.2770300

David B. Dgien, Poovaiah M. Palangappa, N. A. Hunter, Jiayin Li, K. Mohanram

引用次数: 48

HSPICE macromodel of a Programmable Metallization Cell (PMC) and its application to memory design 可编程金属化单元(PMC) HSPICE宏模型及其在存储器设计中的应用

2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2014-07-08 DOI: 10.1145/2770287.2770299

P. Junsangsri, F. Lombardi, Jie Han

引用次数: 7

A new Tunnel-FET based RAM concept for ultra-low power applications 基于隧道场效应管的超低功耗RAM概念

2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2014-07-08 DOI: 10.1145/2770287.2770301

Mostafizur Rahman, Mingyu Li, Jiajun Shi, S. Khasanvis, C. A. Moritz

引用次数: 2

Stochastic reliability evaluation of Sea-of-Tiles based on Double Gate controllable-polarity FETs 基于双栅可控极性场效应管的“瓦片之海”随机可靠性评估

2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2014-07-08 DOI: 10.1145/2770287.2770328

C. Dezan, Sara Zermani

引用次数: 0

Minimization of a reversible quantum 2n-to-n BCD priority encoder 可逆量子2n- n BCD优先编码器的最小化

2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2014-07-08 DOI: 10.1145/2770287.2770307

N. J. Lisa, H. Babu

引用次数: 1

Applications of wavelength-fan-in for high-performance distributed processing systems 波长扇入在高性能分布式处理系统中的应用

2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2014-07-08 DOI: 10.1145/2770287.2770331

A. Tait, P. Prucnal

引用次数: 1

Energy effective 3D stacked hybrid NEMFET-CMOS caches 节能3D堆叠混合NEMFET-CMOS缓存

2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2014-07-08 DOI: 10.1145/2770287.2770324

M. Lefter, M. Enachescu, G. Voicu, S. Cotofana

{"title":"Energy effective 3D stacked hybrid NEMFET-CMOS caches","authors":"M. Lefter, M. Enachescu, G. Voicu, S. Cotofana","doi":"10.1145/2770287.2770324","DOIUrl":"https://doi.org/10.1145/2770287.2770324","url":null,"abstract":"In this paper we propose to utilise 3D-stacked hybrid memories as alternative to traditional CMOS SRAMs in L1 and L2 cache implementations and analyse the potential implications of this approach on the processor performance, measured in terms of Instructions-per-Cycle (IPC) and energy consumption. The 3D hybrid memory cell relies on: (i) a Short Circuit Current Free Nano-Electro-Mechanical Field Effect Transistor (SCCF NEMFET) based inverter for data storage; and (ii) adjacent CMOS-based logic for read/write operations and data preservation. We compare 3D Stacked Hybrid NEMFET-CMOS Caches (3DS-HNCC) of various capacities against state of the art 45 nm low power CMOS SRAM counterparts (2D-CC). All the proposed implementations provide two orders of magnitude static energy reduction (due to NEMFET's extremely low OFF current), a slightly increased dynamic energy consumption, while requiring an approximately 55% larger footprint. The read access time is equivalent, while for write operations it is with about 3 ns higher, as it is dominated by the mechanical movement of the NEMFET's suspended gate. In order to determine if the write latency overhead inflicts any performance penalty, we consider as evaluation vehicle a state of the art mobile out-of-order processor core equipped with 32-kB instruction and data L1 caches, and a unified 2-MB L2 cache. We evaluate different scenarios, utilizing both 3DS-HNCC and 2D-CC at different hierarchy levels, on a set of SPEC 2000 benchmarks. Our simulations indicate that for the considered applications, despite of their increased write access time, 3DS-HNCC L2 caches inflict insignificant IPC penalty while providing, on average, 38% energy savings, when compared with 2D-CC. For L1 instruction caches the IPC penalty is also almost insignificant, while for L1 data caches IPC decreases between 1% to 12% were measured.","PeriodicalId":6519,"journal":{"name":"2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"62 1","pages":"151-156"},"PeriodicalIF":0.0,"publicationDate":"2014-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89208801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Sub-crosspoint RRAM decoding for improved area efficiency 亚交叉点RRAM解码，提高区域效率

2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Pub Date : 2014-07-08 DOI: 10.1145/2770287.2770312

Ravi Patel, E. Friedman

引用次数: 0