Compression architecture for bit-write reduction in non-volatile memory technologies

Abstract

This paper proposes a compression-based architecture for bit-write reduction in emerging non-volatile memories (NVMs). Bit-write reduction has many practical benefits, including lower write latency, lower dynamic energy, and enhanced endurance. The proposed architecture, which is integrated into the NVM module, relies on (i) a frequent pattern compression-decompression engine, (ii) a comparator to reduce bit-writes, and (iii) an opportunistic wear leveler to spread writes and enhance memory endurance by reducing the peak bit-writes/cell. Trace-based simulations of the SPEC CPU2006 benchmarks show a 20× reduction in raw bit-writes on average, which corresponds to a 2-3× improvement over state-of-the-art methods and a 27% reduction in peak cell bit-writes.