Pipeline design in spintronic circuits

Abstract

This paper proposes a latch-less pipeline architecture for spintronic circuits and quantifies the impact of pipeline depth and width on the error rate caused by thermal noise. This paper focuses on concatenable spin logic (CSL) even though the proposed architecture and error rate estimation approach can be applied to any spintronic logic that use magnetic moment of nanomagnets as the computational state variable. The latchless pipeline architecture takes advantage of the non-volatility of nanomagnets and eliminates the need for the extra switches that are necessary in CMOS circuits to latch data at the beginning and end of each pipeline stage. However, choosing a pipeline clock rate requires knowing the circuit delay of a single stage. It is shown that the delay of a magnet can best be represented as a gamma distribution, and thus, in order to achieve a 10-4 error rate with a single switch, the clock period will need to be approximately 120% greater the average delay of a single device. This variation tax can be reduced to under 35% for a circuit with 10 switches connected in series, or it can exceed 145% if the switches are connected in parallel (depth=1).