STT-MRAM based low power synchronous non-volatile logic with timing demultiplexing

Abstract

The high power and long global interconnection delay are two of the major limits for further scaling down of the process nodes in the very large scale integrated (VLSI) systems. Therefore, new technologies and computer architectures are under focused development to reduce the power consumption and interconnection delay. Magnetic tunnel junction (MTJ) nanopillar with the advantages of non-volatility, fast switching speed, and high density promises new designs and architectures to significantly alleviate the power and delay issues. This paper presents new logic-in-memory designs of the basic logic gates based on MTJs, including INV, (N)AND, (N)OR and XOR. The MTJ sharing and timing demultiplexing techniques are used in the proposed non-volatile logic gates to greatly reduce the write power. The simulation results show that the write power of the proposed non-volatile logic gates is as low as 285fJ/bit. The basic logic gates can finish the read operation in less than 160ps with 4.35f J read energy. Moreover, the proposed non-volatile logic gates may be reconfigured after fabrication, which makes the designs more flexible and robust.