半导体技术 Pub Date : 2002-08-07 DOI: 10.1109/ASMC.2002.1001582

C. Gould

引用次数: 3

ABC modeling: advanced features [semiconductor manufacturing] ABC建模:先进特性[半导体制造]

半导体技术 Pub Date : 2002-08-07 DOI: 10.1109/ASMC.2002.1001629

S. Miraglia, C. Blouin, G. Boldman, S. Judd, T. Richardson, D. Yao

引用次数: 5

Advance Process Control solutions for semiconductor manufacturing 先进的半导体制造过程控制解决方案

半导体技术 Pub Date : 2002-08-07 DOI: 10.1109/ASMC.2002.1001583

M. Sarfaty, A. Shanmugasundram, A. Schwarm, J. Paik, Jimin Zhang, R. Pan, M. Seamons, H. Li, R. Hung, S. Parikh

{"title":"Advance Process Control solutions for semiconductor manufacturing","authors":"M. Sarfaty, A. Shanmugasundram, A. Schwarm, J. Paik, Jimin Zhang, R. Pan, M. Seamons, H. Li, R. Hung, S. Parikh","doi":"10.1109/ASMC.2002.1001583","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001583","url":null,"abstract":"Traditional semiconductor manufacturing relies on a fixed process-recipe combined with a classical statistical process control that is used to monitor the production process. Leading-edge manufacturing processes require higher levels of precision and accuracy, which necessitate the use of tighter process control. Advanced Process Control (APC) is becoming a critical component to improve performance, yield, throughput, and flexibility of the manufacturing process using run-to-run, wafer-to-wafer, within wafer and real-time process control. The complexity of device manufacturing process as well as the strong coupling effect of several input parameters on the final process outputs prohibit the use of a classical single variable feedback control method. Therefore, multivariate, model-based APC system is developed in conjunction with feed-forward and feedback mechanisms to automatically determine the optimal recipe for each wafer based on both incoming wafer and tool state properties. The APC system uses wafer metrology, process models and sophisticated control algorithms to provide dynamic fine-tuning of intermediate process targets that enhance final device targets. The design of the APC system enables scalable control solutions across a single chamber, a process tool, multi-tools, a process module and multi-process modules using similar building blocks, concepts and algorithms.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90541016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 21

Water usage reduction in a semiconductor fabricator 在半导体制造中减少用水

半导体技术 Pub Date : 2002-08-07 DOI: 10.1109/ASMC.2002.1001630

G. Klusewitz, J. M. C. Viegh

引用次数: 3

A simulation study on periodical priority dispatching of WIP for product-mix fabrication 混合产品制造中在制品周期优先调度的仿真研究

半导体技术 Pub Date : 2002-08-07 DOI: 10.1109/ASMC.2002.1001569

K. Saito, S. Arima

引用次数: 7

Shallow trench isolation run-to-run control project at Infineon Technologies Richmond 列治文英飞凌技术公司的浅沟隔离运行控制项目

半导体技术 Pub Date : 2002-08-07 DOI: 10.1109/ASMC.2002.1001584

P. Jowett, V. Morozov

{"title":"Shallow trench isolation run-to-run control project at Infineon Technologies Richmond","authors":"P. Jowett, V. Morozov","doi":"10.1109/ASMC.2002.1001584","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001584","url":null,"abstract":"A project was launched to improve Shallow Trench Isolation (STI) etch depth control on magnetically enhanced reactive ion etch (MERIE) chambers. The aim was to reduce the wafer-to-wafer depth variation. The cause of the wafer-to-wafer depth variation was found to be due to a number of factors, including: (a) Multiple chamber/platform of film deposition tools, (b) Multiple Film Thickness Metrology tools, (c) Multiple etch chamber/platform tools and (d) Multiple STI Depth metrology equipment. To account for these variations, a feedback Run-to-Run control loop has been developed. The algorithm utilizes pre-etch film thickness and post-etch STI depth metrology data to output a new etch time for a particular chamber in order to re-center the process. The challenges that where overcome with the Run-to-Run (R2R) algorithm included: (1) Filtering incoming data from possible \"flyers,\" (2) Accounting for uncertainties associated with different metrology tools and (3) Improving the robustness of the control algorithm. After implementation, in-silicon depth standard deviation was reduced to /spl sim/1/3 of its original value. SPC (statistical process control) parameters were also significantly improved.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76596731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Scanner focus and CD response characterization metrology for sub 180 nm lithography 亚180nm光刻的扫描焦点和CD响应特性测量

半导体技术 Pub Date : 2002-08-07 DOI: 10.1109/ASMC.2002.1001638

C. Putnam, H. Magoon, M. Alam, S. Beaumont, C. Fruga, F. Leung, E. Morita, R. Pierce, N. Roberts

引用次数: 1

Advanced Cu CMP defect excursion control for leading edge micro-processor manufacturing 先进的Cu CMP缺陷偏移控制，用于前沿微处理器制造

半导体技术 Pub Date : 2002-08-07 DOI: 10.1109/ASMC.2002.1001581

P. Stöckl, B. Saville, J. Kavanagh, T. Dellwig

{"title":"Advanced Cu CMP defect excursion control for leading edge micro-processor manufacturing","authors":"P. Stöckl, B. Saville, J. Kavanagh, T. Dellwig","doi":"10.1109/ASMC.2002.1001581","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001581","url":null,"abstract":"The introduction of yield sensitive, advanced interconnect technology coupled with the requirement for accelerating yield ramp in today's state-of-the-art semiconductor manufacturing facilities, are driving tool monitoring requirements for fast and accurate defect excursion control. In the Copper CMP module the challenge is accentuated by the relative immaturity of this process, the dominance of single wafer excursions and a high count of nuisance defect types relative to the critical yield-limiting defect types. A manufacturing-worthy Copper CMP tool monitor methodology is described here that improves excursion control through detection and tracking of critical, yield-limiting defect types, independent of non-yield-critical nuisance defect types. High-resolution automatic defect review and classification, a critical component of the methodology, is limited to wafers with high critical-defect counts, reducing monitoring cost and time-to-results. A new trigger sampling feature and intelligent image sampling reduces monitoring cost and time-to-results through minimizing defect review overhead. Integration of such a solution into the manufacturing environment is presented in detail and contrasted next to existing traditional defect excursion control model. Ease-of-use considerations are highlighted with use case examples. The paper will approximate the cost savings to manufacturing such as reducing existing levels of false excursion due to nuisance defects and improving the cycle time in the Cu CMP module. Benefits are achieved by integrating functionality into existing inspection hardware. No additional capital equipment was required.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74071988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Manufacturing implementation of low-k dielectrics for copper damascene technology 低k介电体的制造实施铜大马士革技术

半导体技术 Pub Date : 2002-08-07 DOI: 10.1109/ASMC.2002.1001633

H. Ruelke, C. Streck, J. Hohage, S. Weiher-Telford, O. Chretrien

{"title":"Manufacturing implementation of low-k dielectrics for copper damascene technology","authors":"H. Ruelke, C. Streck, J. Hohage, S. Weiher-Telford, O. Chretrien","doi":"10.1109/ASMC.2002.1001633","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001633","url":null,"abstract":"Advanced logic devices are setting new demands for backend integration. New high-end processor families like the AMD Athlon/sup TM/ and AMD's eighth generation processor (codenamed \"Hammer\"), require the introduction of low-k interlayer dielectric (ILD) materials with copper to enable improvements in chip speed and reduction of overall power consumption. This is a challenging process for both tool suppliers and integrated circuit manufacturers. The semiconductor industry is looking for a low-k solution that delivers easy-to-integrate, high-performance dielectric films combined with high throughput and low cost of ownership. Based on key technical and manufacturing requirements, Advanced Micro Devices, Inc. has chosen the Applied Materials Producer system for low-k dielectric process applications. Implementation of Black Diamond/sup TM/ (BD) and BLOk/sup TM/ into the process flow enables an integrated k value of <3.0, which represents a 20 percent reduction compared to fluorinated silicate glass (F-TEOS) and silicon nitride (SiN). At Fab 30, AMD's advanced copper manufacturing line, the Producer has demonstrated reliable and stable performance in high volume production for the deposition of conventional dielectric films. This paper focuses on bringing a low-k dielectric solution beyond F-TEOS to full manufacturing readiness for copper interconnect technology.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76728793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

The implementation of AFM for process monitoring and metrology in trench MOSFET device manufacturing AFM在沟槽MOSFET器件制造过程监控与计量中的应用

半导体技术 Pub Date : 2002-08-07 DOI: 10.1109/ASMC.2002.1001642

R. Ridley, C. Strate, J. Cumbo, T. Grebs, C. Gasser

引用次数: 5

半导体技术最新文献