2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference最新文献

{"title":"Horizontal systems: Leading technology for next generation HDI production","authors":"S. Kenny, T. Magaya","doi":"10.1109/IMPACT.2009.5382265","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382265","url":null,"abstract":"The developments in high density interconnect, HDI technology are characterized by the following: - Ever higher packaging density. - Reduction in line and space. - New dielectrics to meet high frequency demands. - Employment of thinner substrates. - Environmental and legislative impact. - Requirement for high overall process yields. - Demand for continuous reduction in process costs.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"60 1","pages":"633-636"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82951814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Investigation of parasitic electromagnetic radiation in multilayer packages and MCMs","authors":"R. Arnaudov, Slavi R. Baev, B. Avdjiiski","doi":"10.1109/IMPACT.2009.5382118","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382118","url":null,"abstract":"Electromagnetic radiation from parallel-plate planes of power-return and ground pairs are investigated. Such structures are widely used in microwave multilayer packages, MCMs and could be the source of considerable electromagnetic interference (EMI) or simultaneously switching noise (SSI). Effective methods should be applied for damping and elimination of the radiated fields, especially in small areas and volumes. The developed three-layered LTCC microwave package possesses two separate grounding planes on different layer levels, connected through multiple vias. The estimation of the electromagnetic field distribution — near field, and radiation pattern — far field, are conducted by full-wave analysis. The article also discusses the influence of the layout, vias grid and material properties on the performance of the exemplary structure in the frequency band of interest - 10 to 30 GHz.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"75 1","pages":"286-291"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91097053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Effect of UBM and BCB layers on the thermo-mechanical reliability of wafer level chip scale package (WLCSP)","authors":"Y. S. Chan, S. Lee, F. Song, C. C. Lo, T. Jiang","doi":"10.1109/IMPACT.2009.5382204","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382204","url":null,"abstract":"Cracking of the silicon chip of a wafer level chip scale package (WLCSP) is encountered during a thermal cycle test (TCT). This paper attempts to examine the failure mechanism. Both numerical and experimental efforts were devoted to investigate the problem. A series of finite element models with different combinations of material properties and geometric configurations were developed. The results showed that both the under bump metallization (UBM) and the dielectric layer Benzocyclobuten (BCB) contributed significantly to the stress level induced inside the silicon chip. In addition, solder ball pull tests were performed. The silicon cratering failure mode was reproduced which confirmed the failure mechanism as proposed by the finite element analysis. The effects of all relevant constituent materials on the chip are discussed in detail. Suggestions for the product design improvement are provided at the end of the paper.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"18 1","pages":"407-410"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79133442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Electrochemical corrosion behavior of Pb-free solders for die attachment","authors":"C. Tsai, Jenn-Ming Song, Yen‐Pei Fu","doi":"10.1109/IMPACT.2009.5382213","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382213","url":null,"abstract":"This study aimed to investigate the electrochemical corrosion behavior of the potential Pb-free solders, Bi-11wt%Ag and Zn-40wt%Sn, in 3.5% NaCl solution using the potentiodynamic polarization method with the scanning range from -2000mV to +2000mV. Pb-5wt%Sn alloy was also examined for comparison. Experimental results show that the corrosion potential (Ecorr) decreased in the decreasing order was Bi-11Ag, Pb-5Sn, and Zn-40Sn. Zn-40Sn exhibited the highest current density (Icorr), and that for Pb-5Sn was the lowest. The Pb-5Sn samples had a much extended passive region compared to Bi-11Ag, while the Zn-40Sn samples showed no passive behavior within the scanning range. According to the XPS and XRD data, the corrosion products were main PbCl2 and PbO for Pb-5Sn, BiOCl, AgCl2, and Bi2O3 for Bi-11Ag. Zn rich phases (ZnO and ZnCl2) were found on the polarized surface of Zn-40Sn, and tin oxides were detected at the subsurface.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"41 1","pages":"448-451"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77748910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A comparison study of high-frequency performance between ball bonding and ribbon bonding","authors":"Chien-Cheng Wei, Chin-Ta Fan, Ta-Hsiang Chiang, Ming-Kuen Chiu, S. Ru","doi":"10.1109/IMPACT.2009.5382280","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382280","url":null,"abstract":"This paper presents a comprehensive comparison of high-frequency performance between ball bonding and ribbon bonding. In many microwave applications above 10-GHz, ribbon bonding is usually used because of its high frequency and high power characteristics. In general, ribbon bonding with rectangle-shaped wire will provide lower impedance and inductance at higher frequency than round wire, which also achieve the advantages of stable, less deformation, and low loop height. However these results were not made under a fair comparison between ribbon wire and round wire. In this paper, two objective comparisons for ribbon and round wires have been accomplished under the same conditions on their wire cross-section area and surface area. Therefore, three types of bonding wires, 0.5 × 2 mils ribbon bonding, 2 mils round wire ball/wedge bonding, and 0.8 mils round wire ball bonding were measured up to 20-GHz individually, to analyze their high-frequency characteristics on self-inductance, self-resonant frequency (fSR), and insertion loss (IL) with the same cross-section area and surface area conditions. Based on the measurement results, round wire has lower inductance and IL, and higher fSR compared to ribbon wire when they have the same wire cross-section area. As for the same wire surface area, these three parameters were almost identical for both ribbon and round wires due to the skin effect. It clearly demonstrates that the surface area of conductor determines the current carrying ability instead of the cross section area, and dominates the high-frequency performance of a bonding wire. These experimental results have been systematically compared for verification.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"27 1","pages":"685-688"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77834531","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Response prediction and verification for PCB with package due to thermal and random vibration coupling effects","authors":"Bor-Tsuen Wang, Fu-Xiang Hsu, Xiu-Wei Liang, Chen-Hsiung Hung, Y. Lai, Chang-Lin Yeh, Ying-Chih Lee","doi":"10.1109/IMPACT.2009.5382202","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382202","url":null,"abstract":"The printed circuit board (PCB) subject to vibration and thermal couple loading is of great interest. This work presents both theoretical analysis and experimental verification for the PCB in heating condition subject to random vibration. The designed heating pad is used as the heating source attached to the package on PCB by providing constant temperature inputs. The calibrated finite element model of PCB in fixture condition is employed to perform thermal analysis for the PCB subjected to the fixed high temperature at the package surface. The thermal response of the PCB can be determined, and thus the spectrum response analysis of the PCB including the thermal effect for random excitation according to JEDEC specification is carried out. The temperature distribution over the PCB in heating condition is monitored by the digital infrared thermography and compared with that of finite element analysis (FEA). The acceleration spectral responses on the PCB during random vibration test with thermal effect are also recorded. Results show that the predicted temperature distribution for the heated PCB and acceleration response due to thermal and random vibration compound loadings agree reasonably between the FEA and experiments. The stress fields on the PCB subject to the thermal input and random vibration excitation can then be obtained and evaluated for its possible fatigue failures due to the compound loading effects. This work presents the analytical solutions via the commercial FE code for the PCB subject to compound loadings for thermal input and random vibration excitation. The predicted results are well validated by comparing with experiments. The developed methodology will be beneficial for further study of PCB and its package reliability in considering both thermal and vibration inputs simultaneously.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"1 1","pages":"401-404"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89454934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermal-structural coupled analysis in heating cycle of semiconductor","authors":"Yongtao Chang","doi":"10.1109/IMPACT.2009.5382297","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382297","url":null,"abstract":"A model for RF heated hot wall furnace and a temperature sensor in rapid thermal process is simulated. The mode includes electric induction current, thermal and strain-stress analysis. The model considers a heating cycle and shows temperature variation in wafer, which has reached a stable temperature and then cooled down. And the thermal sensor is compared for inspection the temperature of wafer. Results show the same tendency of temperature variation for the sensor and the wafer, and the sensor radiation has no stable value that should be improved further.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"394 1","pages":"15-17"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76681469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High reliable medium profile copper foil for automobile PCB and IC","authors":"S.C. Lin, C. Tai, K.C. Chen","doi":"10.1109/IMPACT.2009.5382126","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382126","url":null,"abstract":"The Nan Ya MP (Medium Profile) foil is designed to satisfy the market between high roughness HTE foils and low peeling VLP foils. This foil possesses optimum mechanical, physical and chemical properties, which is especially suitable for high reliability application. By the aid of well designed formula, the MP foil breaks the contradiction between low surface roughness and high peel strength. The peel strength of the MP foil is almost the same or even higher than HTE foil, and the surface roughness is lower than HTE foils. In order to achieve the low surface roughness and high peel strength of MP foils, the mountain-type nodule of raw foils are designed to be much lower and shorter, but the number is increased. By special nodule treatment technique, the high density nodules particles are deposited on the surface of MP foil. That is why the MP foils have low surface roughness and high peel strength. Owing to the optimum combination of raw foil and nodule treatment, the MP foils show excellent etching performance. Moreover, even after 250°C X 1hr oven condition, the MP foils almost maintain high tensile strength and elongation, thus the MP foils are much more reliable in high temperature lamination or in other high temperature application field (ie automobile PCB).","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"30 1","pages":"258-260"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76820968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Optimum design of contact springs used in registered jack connectors","authors":"Kun-Nan Chen, Chia-Lin Wu, Hsien-Chie Cheng","doi":"10.1109/IMPACT.2009.5382236","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382236","url":null,"abstract":"Two basis designs of contact springs used in RJ-45 connectors with different layouts and beam thickness were sequentially examined and optimized. The first design failed to attain a feasible solution mainly due to insufficient beam thickness. The second one is simpler in layout and in pin geometry but with thicker pins. Optimum design for Type A and Type B pins based on the second was achieved efficiently using the RSM with the power-transformed response data of computed plastic strain and contact force. Both optimized models of Type A and Type B pins enjoy a reduced strain level and an elevated contact force level above a specified value of 12.5 gf.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"45 10","pages":"529-532"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72620682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fine pitch BGA solder joint split in SMT process","authors":"Chun-Chi Chiu, Yun-Tsung Li, Hsun-Fa Li, Chuei-Tang Wang","doi":"10.1109/IMPACT.2009.5382257","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382257","url":null,"abstract":"Fine pitch(≦0.5mm) BGAs were assembled on many kinds of products for many years, such as Smart Handheld Device, Mobile Phone, Network Device, Notebook main board, etc. Normally the BGA defects are solder joint bridge, solder joint open, and BGA solder joint crack during assembly process. Regarding the solder joint crack, most of cases are caused by external force, such as assembly operation, board testing operation, or unmatched mechanical parts assembly. In our case, we found the BGA solder joint crack is not the same root cause as mentioned above. When we got the two defect PDA (Personal Digital Assistant) devices, we did the FA (Failure Analysis) as usual. The first step, we did the functional test and X-ray analysis again to find the failure symptom. The device could work normally again in functional test by pressing the top of CPU (BGA package). We also performed CSA (Cross Section Analysis) and dye and pry test to realize the defect is BGA solder joint crack. Regarding the result, we suspected that the crack might not be caused by external force due to the crack did not locate at the corner or outer row of BGA. But we still can't identify which process or operation to cause the defect. At the same time, we had sorted more same defect boards from our stock. We determined this is not the single case. So, we had three directions to analyze. For material, we had performed push test, CSA and EDS (Energy Dispersive Spectrometer) to verify the solder ball due to the solder crack was at BGA package side. For process, we had conducted two experiments to find out the suspected station and operation. From our experiment result, we had two conclusions. One is the defect could not be eliminated by changing the reflow parameters or the type of reflow oven, the other is the defect occurred in 2nd side SMT process. So, to change the process sequence would be the short-term solution to prevent the defect happen again before we find out the root cause. We also found the defects located at some specific points from our experiment result. Then we focused on the relationship between crack locations and PCB design and found that every crack solder joint has buried via beneath it. It means the buried via is the major cause of solder joint crack during SMT process. So, we had analyzed the structure and filling material of buried via of HDI (High Density Interconnect) PCB. We found the different CTE (Coefficient of Thermal Expansion) between PCB and buried via filling material would caused thermal stress remain around the BGA solder joint by CAE (Computer- Aided Engineering) simulation. When the fine pitch BGA solder joint was proceeded into 2nd side SMT reflow, the thermal stress will split the BGA solder joint. So, how to eliminate the thermal stress will be the solution for BGA solder joint split. Referring to the article for more details discussed.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"16 1","pages":"602-605"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75181061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}