2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059)最新文献

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Analysis of detrap current due to oxide traps to improve flash memory retention 分析氧化陷阱引起的陷阱电流,以提高闪存的保留
R. Yamada, Y. Mori, Y. Okuyama, J. Yugami, T. Nishimoto, H. Kume
{"title":"Analysis of detrap current due to oxide traps to improve flash memory retention","authors":"R. Yamada, Y. Mori, Y. Okuyama, J. Yugami, T. Nishimoto, H. Kume","doi":"10.1109/RELPHY.2000.843915","DOIUrl":"https://doi.org/10.1109/RELPHY.2000.843915","url":null,"abstract":"To improve flash memory retention characteristics, we study detrap current due to oxide traps in metal-oxide-semiconductor structures (MOS capacitors and MOSFETs). We show that threshold voltage shift due to detrap current in flash memories can reach 0.6 V for 1 year. This value is detrimental for flash memory retention. Next, we analyze the two types of conduction mechanism of the detrap current, which are direct tunneling to the anode from deeper traps and thermally excited electron tunneling to the oxide conduction band from shallower traps. The deeper traps are generated by electron injection during Fowler-Nordheim stressing, while the shallower traps are generated by hole injection.","PeriodicalId":6387,"journal":{"name":"2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75365851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 60
Experimental data and statistical models for bimodal EM failures 双峰电磁失效的实验数据和统计模型
A. Fischer, A. Abel, M. Lepper, A. Zitzelsberger, A. von Glasow
{"title":"Experimental data and statistical models for bimodal EM failures","authors":"A. Fischer, A. Abel, M. Lepper, A. Zitzelsberger, A. von Glasow","doi":"10.1109/RELPHY.2000.843940","DOIUrl":"https://doi.org/10.1109/RELPHY.2000.843940","url":null,"abstract":"The correct model for the electromigration failure distribution is a key issue in reliability methodology. Usually, the failure times of a sample are fitted by a single log-normal distribution. However, in some cases relevant deviations can be found. In this paper two types of non-log-normal distributions observed on via-line structures are discussed. They can be modeled by two types of bimodal distributions, each composed of two log-normal distributions. Both models consider different failure mechanisms within the sample or specimen. Experimental data sets coinciding with either model will be presented. The physical failure analysis confirms the model assumptions and supports the bimodal distribution concept.","PeriodicalId":6387,"journal":{"name":"2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80249445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 33
Bias and temperature stress reliability of InGaP/GaAs HBTs InGaP/GaAs HBTs的偏置和温度应力可靠性
A. Rezazadeh, S. Bashar, H. Sheng, F. Amin, L. Cattani, J. Liou
{"title":"Bias and temperature stress reliability of InGaP/GaAs HBTs","authors":"A. Rezazadeh, S. Bashar, H. Sheng, F. Amin, L. Cattani, J. Liou","doi":"10.1109/RELPHY.2000.843923","DOIUrl":"https://doi.org/10.1109/RELPHY.2000.843923","url":null,"abstract":"The reliability of InGaP/GaAs N-p-n HBTs with different base metal contact systems (Au/Zn/Au, Ti/Au, Ti/Pt/Au and the novel Ti/ZrB/sub 2//Au) under current and temperature stress is studied in this paper. We further report results of current stress on three p-GaAs doping impurities namely Zn, Be- and C. The effect of O/sup +//H/sup +/ and O/sup +//He/sup +/ ions, used in the fabrication of planar self-aligned HBTs, is also investigated in the stability of device dc current gain. The instability phenomena typical of each factor and their effects on the HBT characteristics are reported.","PeriodicalId":6387,"journal":{"name":"2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83789200","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Tunneling current characteristics and oxide breakdown in P+ poly gate PFET capacitors P+多栅极pet电容器的隧道电流特性和氧化物击穿
J. McKenna, E. Wu, S. Lo
{"title":"Tunneling current characteristics and oxide breakdown in P+ poly gate PFET capacitors","authors":"J. McKenna, E. Wu, S. Lo","doi":"10.1109/RELPHY.2000.843885","DOIUrl":"https://doi.org/10.1109/RELPHY.2000.843885","url":null,"abstract":"In this work, we investigate both tunneling current and oxide breakdown characteristics for lightly and heavily doped p+ polysilicon gates of PFET capacitors in inversion mode. It was found that tunneling currents show significantly different magnitude for the two doping conditions over the same applied gate voltages. We present experimental evidence that strongly supports electron energy, as set by the gate voltage, and electron fluence, measured as charge-to-breakdown, Q/sub BD/, as being the physical parameters that control the breakdown process, rather than oxide field and time-to-breakdown, T/sub BD/, as suggested by the thermo-chemical model.","PeriodicalId":6387,"journal":{"name":"2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81175419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
Experimental evidence for voltage driven breakdown models in ultrathin gate oxides 超薄栅极氧化物中电压驱动击穿模型的实验证据
P. Nicollian, W. Hunter, J.C. Hu
{"title":"Experimental evidence for voltage driven breakdown models in ultrathin gate oxides","authors":"P. Nicollian, W. Hunter, J.C. Hu","doi":"10.1109/RELPHY.2000.843884","DOIUrl":"https://doi.org/10.1109/RELPHY.2000.843884","url":null,"abstract":"We have performed an experiment proving that the widely accepted E-field TDDB model is a physically incorrect description of breakdown in ultrathin gate oxides. Although interface traps are the dominant SILC mechanism below 5 V stress, breakdown remains limited by bulk trap generation and is voltage-driven. It has been recently proposed that the anode hole injection model is still operative at low voltages. Although we will show that holes do generate bulk traps and cause breakdown in ultrathin oxides, hole injection does not completely account for all of the trap generation mechanisms observed during direct tunneling stress.","PeriodicalId":6387,"journal":{"name":"2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91284453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 122
Silicon technology directions in the new millennium 新千年的硅技术方向
T. Ning
{"title":"Silicon technology directions in the new millennium","authors":"T. Ning","doi":"10.1109/RELPHY.2000.843883","DOIUrl":"https://doi.org/10.1109/RELPHY.2000.843883","url":null,"abstract":"Silicon technology development is at a crossroad, in spite of its exponential rate of progress for more than thirty years. It is now clear that traditional CMOS devices are fast approaching both performance saturation and density saturation. Nonetheless, CMOS will remain the digital logic technology platform for future evolution of silicon technology in application-specific directions. Besides optimizing CMOS scaling further for speed and density, there will be additional emphases placed upon low power dissipation, on programmability, RF and analog functions, and on the chip-scale integration of these functions with digital CMOS. The technical challenges are formidable, but the application opportunities enabled by these developments will provide the incentive for driving the development of silicon technology forward.","PeriodicalId":6387,"journal":{"name":"2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91358971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Electrical probing of deep sub-micron ICs using scanning probes 用扫描探针对深亚微米集成电路进行电探测
K. Krieg, R. Qi, D. Thomson, G. Bridges
{"title":"Electrical probing of deep sub-micron ICs using scanning probes","authors":"K. Krieg, R. Qi, D. Thomson, G. Bridges","doi":"10.1109/RELPHY.2000.843946","DOIUrl":"https://doi.org/10.1109/RELPHY.2000.843946","url":null,"abstract":"A contact electrical probe for imaging and real-time signal measurement of deep sub-micron integrated circuits is presented. Similar to wire probers, the probe operates on a standard probe-station, but utilizes a conductive atomic force microscope micromachined tip to rapidly measure surface topography and acquire real-time high-frequency signals. The probe scanning system enables imaging and placement on features as small as 0.18 micron and is able to control and maintain the contact force to less than 50 nanonewton, thus minimizing circuit damage. The probe tip incorporates active electronics near the tip enabling 300 MHz bandwidth measurements while presenting a high impedance load, less than 120 fF, to the device being measured. Measurements of 0.25 /spl mu/m interconnects and polished devices is presented.","PeriodicalId":6387,"journal":{"name":"2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73604992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Electromigration lifetime enhancement for lines with multiple branches 多支路线路的电迁移寿命增强
Michael J. Dion
{"title":"Electromigration lifetime enhancement for lines with multiple branches","authors":"Michael J. Dion","doi":"10.1109/RELPHY.2000.843934","DOIUrl":"https://doi.org/10.1109/RELPHY.2000.843934","url":null,"abstract":"With clock or power supply interconnect \"trees\" there is often a very high current \"trunk\" feeding current to multiple branches. This work demonstrates and discusses increased \"trunk\" lifetime with increasing numbers of current branches in a plug-via metal system. The branches act as reservoirs or sources of additional Al and Cu ions, which can re-fill portions of voids and/or slow void growth. It is discussed that any area of metal at a lower current density might be considered a reservoir or source of metal ions for higher current density regions, and can effectively extend the lifetime of the higher current density region. Comparative Black's model parameters are developed and failure analysis is described.","PeriodicalId":6387,"journal":{"name":"2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86501922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
The role of the spacer oxide in determining worst-case hot-carrier stress conditions for NMOS LDD devices 间隔氧化物在确定NMOS LDD器件最坏情况下热载流子应力条件中的作用
E. E. King, R. Lacoe, J. Wang-Ratkovic
{"title":"The role of the spacer oxide in determining worst-case hot-carrier stress conditions for NMOS LDD devices","authors":"E. E. King, R. Lacoe, J. Wang-Ratkovic","doi":"10.1109/RELPHY.2000.843895","DOIUrl":"https://doi.org/10.1109/RELPHY.2000.843895","url":null,"abstract":"In this paper the underlying mechanisms that produce the crossover in worst-case hot-carrier stress condition observed at room temperature in some deep submicron lightly-doped-drain (LDD) NMOS devices and at cryogenic temperatures for devices with longer channel lengths are investigated. Experiments were performed that demonstrate the generality of the cross-over. The role of stress temperature, measurement temperature and stress condition were experimentally addressed. The temperature dependence of the mobility was measured, and an analysis is presented that shows that mobility changes alone do not explain the observed changes in the transconductance. A model is proposed that allows for changes in the source-drain resistance with stress time. It is suggested that the origin of the time-dependent increasing source-drain resistance was the injection of charge, either in the form of fixed charge or as interface states, into the spacer oxide above the LDD region. This model is used to explain the qualitative dependence of the worst-case stress condition on channel length and temperature. Finally, it is suggested that the methodology used to design the LDD structure be modified to account for these new observations.","PeriodicalId":6387,"journal":{"name":"2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79535597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Generation of hot carriers by secondary impact ionization in deep submicron devices: model and light emission characterization 在深亚微米器件中通过二次冲击电离产生热载流子:模型和光发射特性
B. Marchand, D. Blachier, C. Leroux, G. Ghibaudo, F. Balestra, G. Reimbold
{"title":"Generation of hot carriers by secondary impact ionization in deep submicron devices: model and light emission characterization","authors":"B. Marchand, D. Blachier, C. Leroux, G. Ghibaudo, F. Balestra, G. Reimbold","doi":"10.1109/RELPHY.2000.843896","DOIUrl":"https://doi.org/10.1109/RELPHY.2000.843896","url":null,"abstract":"This paper gives a deep insight on the secondary impact ionization phenomenon. A simple and accurate analytical model of the gate current in deep sub-micron MOS devices is presented, taking into account the substrate bias and the temperature influence. Also for the first time, the related light emission is analyzed. The spectrum analysis is shown to allow individual observation of both first and secondary impact ionizations. Secondary ionization is shown to correlate to substrate current. The photon origin is discussed.","PeriodicalId":6387,"journal":{"name":"2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91435706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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