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Intrinsic graphene/metal contact 固有石墨烯/金属接触
2012 International Electron Devices Meeting Pub Date : 2012-12-01 DOI: 10.1109/IEDM.2012.6478975
K. Nagashio, R. Ifuku, T. Moriyama, T. Nishimura, A. Toriumi
{"title":"Intrinsic graphene/metal contact","authors":"K. Nagashio, R. Ifuku, T. Moriyama, T. Nishimura, A. Toriumi","doi":"10.1109/IEDM.2012.6478975","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6478975","url":null,"abstract":"This paper presents our recent understanding of metal/graphene contact in terms of intrinsic interface obtained from the comparison between resist-free and conventional EB processes, and discusses future challenges to reduce the contact resistivity.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"32 1","pages":"4.1.1-4.1.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83694131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Current fluctuation in sub-nano second regime in gate-all-around nanowire channels studied with ensemble Monte Carlo/molecular dynamics simulation 用集合蒙特卡罗/分子动力学模拟研究了栅极全纳米线通道亚纳秒区电流波动
2012 International Electron Devices Meeting Pub Date : 2012-12-01 DOI: 10.1109/IEDM.2012.6479058
T. Kamioka, H. Imai, Y. Kamakura, K. Ohmori, K. Shiraishi, M. Niwa, K. Yamada, T. Watanabe
{"title":"Current fluctuation in sub-nano second regime in gate-all-around nanowire channels studied with ensemble Monte Carlo/molecular dynamics simulation","authors":"T. Kamioka, H. Imai, Y. Kamakura, K. Ohmori, K. Shiraishi, M. Niwa, K. Yamada, T. Watanabe","doi":"10.1109/IEDM.2012.6479058","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479058","url":null,"abstract":"The impact of current fluctuation due to discreteness in carrier numbers on high-frequency noise amplitudes is numerically investigated, focusing on the comparison to the impact of a single trapped charge in the oxide layer for gate-all-around nanowire structures. The variation in the amount of the charge transporting through the channel within a single clock cycle is estimated. The transported charge variation due to the current fluctuation clearly shows the universality with respect to the total amount of the transported charge. It concludes that the current fluctuation becomes a dominant noise source over 100 GHz range.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"32 1","pages":"17.2.1-17.2.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81901810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Scaling directions for 2D and 3D NAND cells 2D和3D NAND单元的缩放方向
2012 International Electron Devices Meeting Pub Date : 2012-12-01 DOI: 10.1109/IEDM.2012.6478961
A. Goda, K. Parat
{"title":"Scaling directions for 2D and 3D NAND cells","authors":"A. Goda, K. Parat","doi":"10.1109/IEDM.2012.6478961","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6478961","url":null,"abstract":"This paper describes NAND cell scaling directions for 20nm and beyond. Many of the 2D NAND cell scaling challenges can be resolved by a planar floating gate (FG) cell. Scaling directions and key technology requirements for 3D NAND are also discussed.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"3 1","pages":"2.1.1-2.1.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86386820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 69
Room-temperature photonic crystal nanocavity light emitting diodes based on Ge self-assembled quantum dots 基于锗自组装量子点的室温光子晶体纳米腔发光二极管
2012 International Electron Devices Meeting Pub Date : 2012-12-01 DOI: 10.1109/IEDM.2012.6479115
Xuejun Xu, T. Maruizumi, Y. Shiraki
{"title":"Room-temperature photonic crystal nanocavity light emitting diodes based on Ge self-assembled quantum dots","authors":"Xuejun Xu, T. Maruizumi, Y. Shiraki","doi":"10.1109/IEDM.2012.6479115","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479115","url":null,"abstract":"Current-injected light emitting diodes (LEDs) based on Ge self-assembled quantum dots embedded in photonic crystal (PhC) nanocavities are demonstrated by using a lateral PIN diode. Strong resonant electroluminescence (EL) is obtained at room-temperature when the injected current is larger than 50 μA. Sharp resonant peaks corresponding to the PhC cavity modes, with Q-factor larger than 800, are observed in the EL spectrum. The current dependence of the light emission properties is also discussed. By collecting the light emission through a single-mode fiber, we measure the output power of the LED to be about 6 pW under 3 mA injected current.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"12 1","pages":"27.4.1-27.4.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88234700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Polarity control in double-gate, gate-all-around vertically stacked silicon nanowire FETs 双栅极、栅极全方位垂直堆叠硅纳米线场效应管的极性控制
2012 International Electron Devices Meeting Pub Date : 2012-12-01 DOI: 10.1109/IEDM.2012.6479004
M. D. Marchi, D. Sacchetto, Stefano Frache, Jian Zhang, P. Gaillardon, Yusuf Leblebici, G. D. Micheli
{"title":"Polarity control in double-gate, gate-all-around vertically stacked silicon nanowire FETs","authors":"M. D. Marchi, D. Sacchetto, Stefano Frache, Jian Zhang, P. Gaillardon, Yusuf Leblebici, G. D. Micheli","doi":"10.1109/IEDM.2012.6479004","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479004","url":null,"abstract":"We fabricated and characterized new ambipolar silicon nanowire (SiNW) FET transistors featuring two independent gate-all-around electrodes and vertically stacked SiNW channels. One gate electrode enables dynamic configuration of the device polarity (n or p-type), while the other switches on/off the device. Measurement results on silicon show Ion/Ioff > 106 and S ≈ 64mV/dec (70mV/dec) for p(n)-type operation in the same device. We show that XOR operation is embedded in the device characteristic, and we demonstrate for the first time a fully functional 2-transistor XOR gate.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"1 1","pages":"8.4.1-8.4.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88369826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 237
New observations on AC NBTI induced dynamic variability in scaled high-κ/Metal-gate MOSFETs: Characterization, origin of frequency dependence, and impacts on circuits 交流NBTI诱导的高κ/金属栅极mosfet的动态变化的新观察:表征，频率依赖的来源，以及对电路的影响
2012 International Electron Devices Meeting Pub Date : 2012-12-01 DOI: 10.1109/IEDM.2012.6479075
Changze Liu, P. Ren, Runsheng Wang, Ru Huang, Jiaojiao Ou, Qianqian Huang, Jibin Zou, Jianping Wang, Jingang Wu, Shaofeng Yu, Hanming Wu, Shiuh-Wuu Lee, Yangyuan Wang
{"title":"New observations on AC NBTI induced dynamic variability in scaled high-κ/Metal-gate MOSFETs: Characterization, origin of frequency dependence, and impacts on circuits","authors":"Changze Liu, P. Ren, Runsheng Wang, Ru Huang, Jiaojiao Ou, Qianqian Huang, Jibin Zou, Jianping Wang, Jingang Wu, Shaofeng Yu, Hanming Wu, Shiuh-Wuu Lee, Yangyuan Wang","doi":"10.1109/IEDM.2012.6479075","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479075","url":null,"abstract":"In this paper, the frequency dependence of the dynamic variation induced by AC NBTI aging in scaled high-κ/metal-gate devices are experimentally studied for the first time. Challenges in comprehensively characterizing AC NBTI induced variation are addressed by the modified method. The additional variation source in AC NBTI, originating from the variations among each AC clock cycle, is found to be non-negligible and thus should be included in predicting circuit stability. With increasing AC frequency, the mean value (μ) of the Vth shift (ΔVth) is reduced as expected; however, the variation (σ) of ΔVth is almost unchanged, which surprisingly disagrees with the conventional model predicting the reduced variation. The origin of this new observation is found due to the competitive impacts of the activated trap number and the trap occupancy probability during device aging. Taken clock-CCV and frequency dependence into account, the impacts of AC NBTI on the SRAM cell stability can be evaluated in terms of both degradation and variation. The results are helpful for the future variability-aware circuit design.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"33 1","pages":"19.5.1-19.5.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88374231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
50% Efficiency intermediate band solar cell design using highly periodical silicon nanodisk array 采用高周期硅纳米盘阵列设计50%效率中间带太阳能电池
2012 International Electron Devices Meeting Pub Date : 2012-12-01 DOI: 10.1109/IEDM.2012.6478987
Weiguo Hu, M. Igarashi, Ming-Yi Lee, Yiming Li, S. Samukawa
{"title":"50% Efficiency intermediate band solar cell design using highly periodical silicon nanodisk array","authors":"Weiguo Hu, M. Igarashi, Ming-Yi Lee, Yiming Li, S. Samukawa","doi":"10.1109/IEDM.2012.6478987","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6478987","url":null,"abstract":"A high-quality Si nanodisk superlattice is fabricated by our top-down process. For the first time, a 3D finite element method (FEM) is developed to calculate energy band structure, optical and electrical properties, as well as the intermediate band solar cell (IBSC) operation for the realistic structure. Both the experiments and simulations reveal that miniband formation enhances the optical and electrical collections. Consequently, detailed electronic structure and conversion efficiency are examined to guide optimal design of minibands. A theoretically predicted maximal efficiency of the explored Si nanodisk superlattice is 50.3%, which is promising, compared with well-known complicated Si tandem solar cells.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"37 1","pages":"6.1.1-6.1.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88959703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Electrical performances of junctionless-FETs at the scaling limit (LCH = 3 nm) 无结场效应管在缩放极限(LCH = 3 nm)下的电学性能
2012 International Electron Devices Meeting Pub Date : 2012-12-01 DOI: 10.1109/IEDM.2012.6479006
S. Migita, Y. Morita, M. Masahara, H. Ota
{"title":"Electrical performances of junctionless-FETs at the scaling limit (LCH = 3 nm)","authors":"S. Migita, Y. Morita, M. Masahara, H. Ota","doi":"10.1109/IEDM.2012.6479006","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479006","url":null,"abstract":"Junctionless-FETs (JL-FET) with extremely short channel length (LCH = 3 nm) were fabricated using anisotropic wet etching of SOI substrate, and superior transfer characteristics are demonstrated. Experimental results and simulation study predict that ultra-low voltage CMOS can be constructed using N- and P-type JL-FETs with single work function metal gate. Furthermore, it is cleared that carrier velocity in the short channel JL-FET is approaching to the injection velocity.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"1 1","pages":"8.6.1-8.6.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89101239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 43
Design innovations to optimize the 3D stackable vertical gate (VG) NAND flash 设计创新优化3D可堆叠垂直栅(VG) NAND闪存
2012 International Electron Devices Meeting Pub Date : 2012-12-01 DOI: 10.1109/IEDM.2012.6479015
Chun-Hsiung Hung, H. Lue, Shuo-Nan Hung, C. Hsieh, Kuo-Pin Chang, Ti-Wen Chen, Shih-Lin Huang, Tzung Shen Chen, Chih-Shen Chang, Wen-Wei Yeh, Y. Hsiao, Chieh-Fang Chen, Shih-Cheng Huang, Yan-Ru Chen, Guan-Ru Lee, Chih-Wei Hu, Shih-Hung Chen, C. Chiu, Y. Shih, Chih-Yuan Lu
{"title":"Design innovations to optimize the 3D stackable vertical gate (VG) NAND flash","authors":"Chun-Hsiung Hung, H. Lue, Shuo-Nan Hung, C. Hsieh, Kuo-Pin Chang, Ti-Wen Chen, Shih-Lin Huang, Tzung Shen Chen, Chih-Shen Chang, Wen-Wei Yeh, Y. Hsiao, Chieh-Fang Chen, Shih-Cheng Huang, Yan-Ru Chen, Guan-Ru Lee, Chih-Wei Hu, Shih-Hung Chen, C. Chiu, Y. Shih, Chih-Yuan Lu","doi":"10.1109/IEDM.2012.6479015","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479015","url":null,"abstract":"The design architecture for 3D vertical gate (VG) NAND Flash is discussed in detail. With the unique structure of 3D VG and its decoding method, we have developed several important design innovations to optimize this technology: (1) “Shift-BL scramble” to average the BL capacitances, providing uniform CBL's for various memory layers; (2) Optimized read waveforms to suppress the hot-carrier induced read disturb in the page reading mode; (3) Novel reverse read with “multi-Vt sensing technique” for different memory layers to compensate the Vt variation due to the layer-to-layer process difference; (4) Program inhibit method and technique to minimize the “Z-directional” self-boosting program disturb in 3D stackable memory. Optimized chip-level performances with excellent memory window for SLC and MLC operations are demonstrated on a 2-layer 3D VG NAND chip.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"71 1","pages":"10.1.1-10.1.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88901903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Electrode/oxide interface engineering by inserting single-layer graphene: Application for HfOx-based resistive random access memory 插入单层石墨烯的电极/氧化物界面工程:在基于hfox的电阻随机存取存储器中的应用
2012 International Electron Devices Meeting Pub Date : 2012-12-01 DOI: 10.1109/IEDM.2012.6479081
Hong-Yu Chen, H. Tian, B. Gao, Shimeng Yu, Jiale Liang, Jinfeng Kang, Yuegang Zhang, T. Ren, H. Wong
{"title":"Electrode/oxide interface engineering by inserting single-layer graphene: Application for HfOx-based resistive random access memory","authors":"Hong-Yu Chen, H. Tian, B. Gao, Shimeng Yu, Jiale Liang, Jinfeng Kang, Yuegang Zhang, T. Ren, H. Wong","doi":"10.1109/IEDM.2012.6479081","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479081","url":null,"abstract":"Electrode/oxide interface with inserted single-layer graphene (SLG) increases low resistance state (LRS) resistance (> 1MΩ) due to its intrinsically high out-of-plane resistance in HfOx-based resistive random access memory (RRAM). This interface engineering technique enables the reduction of the RESET current by 22 times and the programming power consumption by 47 times. The interface between oxide layer and metal electrode is studied using Ramen spectroscopy coupled with electrical measurement. Raman mapping and single point measurements show noticeable changes in both D-band and G-band signals of SLG during electrical cycling. This observation suggests a possible interaction of oxygen migrated from the metal oxide with the graphene. This work illustrates that interface engineering design plays an important role for RRAM material selection in addition to exploring different metal oxides or metal electrode materials for RRAM.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"30 1","pages":"20.5.1-20.5.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73315636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
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