{"title":"无结场效应管在缩放极限(LCH = 3 nm)下的电学性能","authors":"S. Migita, Y. Morita, M. Masahara, H. Ota","doi":"10.1109/IEDM.2012.6479006","DOIUrl":null,"url":null,"abstract":"Junctionless-FETs (JL-FET) with extremely short channel length (LCH = 3 nm) were fabricated using anisotropic wet etching of SOI substrate, and superior transfer characteristics are demonstrated. Experimental results and simulation study predict that ultra-low voltage CMOS can be constructed using N- and P-type JL-FETs with single work function metal gate. Furthermore, it is cleared that carrier velocity in the short channel JL-FET is approaching to the injection velocity.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"1 1","pages":"8.6.1-8.6.4"},"PeriodicalIF":0.0000,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"43","resultStr":"{\"title\":\"Electrical performances of junctionless-FETs at the scaling limit (LCH = 3 nm)\",\"authors\":\"S. Migita, Y. Morita, M. Masahara, H. Ota\",\"doi\":\"10.1109/IEDM.2012.6479006\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Junctionless-FETs (JL-FET) with extremely short channel length (LCH = 3 nm) were fabricated using anisotropic wet etching of SOI substrate, and superior transfer characteristics are demonstrated. Experimental results and simulation study predict that ultra-low voltage CMOS can be constructed using N- and P-type JL-FETs with single work function metal gate. Furthermore, it is cleared that carrier velocity in the short channel JL-FET is approaching to the injection velocity.\",\"PeriodicalId\":6376,\"journal\":{\"name\":\"2012 International Electron Devices Meeting\",\"volume\":\"1 1\",\"pages\":\"8.6.1-8.6.4\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"43\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 International Electron Devices Meeting\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.2012.6479006\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 International Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2012.6479006","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Electrical performances of junctionless-FETs at the scaling limit (LCH = 3 nm)
Junctionless-FETs (JL-FET) with extremely short channel length (LCH = 3 nm) were fabricated using anisotropic wet etching of SOI substrate, and superior transfer characteristics are demonstrated. Experimental results and simulation study predict that ultra-low voltage CMOS can be constructed using N- and P-type JL-FETs with single work function metal gate. Furthermore, it is cleared that carrier velocity in the short channel JL-FET is approaching to the injection velocity.