Scaling directions for 2D and 3D NAND cells

2012 International Electron Devices Meeting Pub Date : 2012-12-01 DOI:10.1109/IEDM.2012.6478961

A. Goda, K. Parat

引用次数: 69

Abstract

This paper describes NAND cell scaling directions for 20nm and beyond. Many of the 2D NAND cell scaling challenges can be resolved by a planar floating gate (FG) cell. Scaling directions and key technology requirements for 3D NAND are also discussed.

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2D和3D NAND单元的缩放方向

本文描述了NAND电池在20nm及以上的缩放方向。许多二维NAND单元的缩放挑战可以通过平面浮栅(FG)单元来解决。讨论了三维NAND的缩放方向和关键技术要求。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2012 International Electron Devices Meeting

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