2008 International Conference on Electronic Packaging Technology & High Density Packaging最新文献_第5页

Novel low-temperature micro-insert bonding technology for 3D package 新型3D封装低温微插入键合技术

2008 International Conference on Electronic Packaging Technology & High Density Packaging Pub Date : 2008-07-28 DOI: 10.1109/ICEPT.2008.4606956

Po Xu, A. Hu, Zhuo Chen, Ming Li, D. Mao

引用次数: 1

Reliability study of flexible display module by experiments 柔性显示模块可靠性实验研究

2008 International Conference on Electronic Packaging Technology & High Density Packaging Pub Date : 2008-07-28 DOI: 10.1109/ICEPT.2008.4607161

Q. Chen, Leon Xu, A. Salo, Gustavo Neto, Germano Freitas

引用次数: 17

Parametric study on board-level electronic test device subjected to JEDEC vibration loads JEDEC振动载荷下板级电子测试装置的参数化研究

2008 International Conference on Electronic Packaging Technology & High Density Packaging Pub Date : 2008-07-28 DOI: 10.1109/ICEPT.2008.4607140

Chang-Lin Yeh, Y. Lai, Ching-Chun Wang

引用次数: 3

A design for increasing the immunity to RFI of protection IC of lithium-ion battery 一种提高锂离子电池保护IC抗射频干扰能力的设计

2008 International Conference on Electronic Packaging Technology & High Density Packaging Pub Date : 2008-07-28 DOI: 10.1109/ICEPT.2008.4607159

Dongfang Cheng, Jue Zhang, Xiaohui Li, Jiongming Wang

引用次数: 1

C4NP for Pb-free solder wafer bumping and 3D fine-pitch applications C4NP用于无铅焊料晶圆碰撞和3D细间距应用

2008 International Conference on Electronic Packaging Technology & High Density Packaging Pub Date : 2008-07-28 DOI: 10.1109/ICEPT.2008.4607052

D. Shih, B. Dang, P. Gruber, M. Lu, S. Kang, S. Buchwalter, J. Knickerbocker, E. Perfecto, J. Garant, S. Knickerbocker, K. Semkow, B. Sundlof, J. Busby, R. Weisman, K. Ruhmer, E. Hughlett

{"title":"C4NP for Pb-free solder wafer bumping and 3D fine-pitch applications","authors":"D. Shih, B. Dang, P. Gruber, M. Lu, S. Kang, S. Buchwalter, J. Knickerbocker, E. Perfecto, J. Garant, S. Knickerbocker, K. Semkow, B. Sundlof, J. Busby, R. Weisman, K. Ruhmer, E. Hughlett","doi":"10.1109/ICEPT.2008.4607052","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4607052","url":null,"abstract":"Controlled collapse chip connection - new process (C4NP) technology is a novel solder bumping technology developed by IBM to address the limitations of existing bumping technologies. Through continuous improvements in processes, materials and defect control, C4NP technology has been successfully implemented at IBM in the manufacturing of all 300 mm Pb-free solder bumped wafers. Both 200 mum and 150 mum pitch products have been qualified and are currently ramping up volume production. Extendibility of C4NP to 50 mum ultra-fine pitch microbump application has been successfully demonstrated with the existing C4NP manufacturing tools. Targeted applications for microbumps are three-dimensional (3D) chip integration and the conversion of memory wafers from wirebonding (WB) to C4 bumping. The metrology data on solder volume, bump height, defect and yield have been characterized by RVSI inspection. This paper reviews the C4NP processes from mold manufacturing, solder fill and solder transfer onto 300 mm wafers, along with defect and yield analysis. Reliability challenges as well as solutions in the development and qualification of flip chip Pb-free solder joint are also reviewed. In addition to a suitable under bump metallurgy (UBM), a robust lead-free solder alloy with precisely controlled composition and special alloy doping is needed to enhance performance and reliability.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":"39 1","pages":"1-7"},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77096089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Design advisor for package-on-package (PoP) manufacturing 包对包(PoP)制造的设计顾问

2008 International Conference on Electronic Packaging Technology & High Density Packaging Pub Date : 2008-07-28 DOI: 10.1109/ICEPT.2008.4606950

B. Xie, P. Sun, D. Shi

{"title":"Design advisor for package-on-package (PoP) manufacturing","authors":"B. Xie, P. Sun, D. Shi","doi":"10.1109/ICEPT.2008.4606950","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4606950","url":null,"abstract":"The needs to integrate devices into portable products with smaller form factor and more functionality have fueled enormous growth of 3D packaging technology. The package-on-package (PoP) is one of the 3D packaging solutions, by which the packaging and assembly houses can achieve a lower cost, faster turn benefits and testing prior to assembly. PoP is a complicated system with multi-layered structure, which induces more manufacturability issues, such as stand-off height issue and top & bottom packages having different types of warpage. In order to reduce R&D cost, achieve fast time-to-market and address most of the manufacturability issues during the development of a new PoP, a design advisor for PoP manufacturing has been developed based on the design for manufacturability (DFM) methodology. The key components of this design advisor are the validated numerical models, comprehensive materials library, design guidelines of PoP packaging and novel finite element analysis (FEA) techniques. With the developed novel FEA techniques for curing process simulation and seamless packaging process simulation, complete numerical models for PoP manufacturing were developed and validated, which can simulate the whole PoP manufacturing processes. The design advisor is easy to use by selecting package geometries, material properties and process parameters. By running the envelope-based design advisor for normal package design or the FEA-based design advisor for special package design, the detailed analysis reports can be generated, including simulation results, design evaluations and recommendations to ensure the first-time success of package design. Therefore, the design advisor can help improve the yield of complex PoP manufacturing processes leading to higher quality and confidence of manufacturing processes, faster time-to-market and lower overall manufacturing cost.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":"30 1","pages":"1-7"},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76828155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Study on non-uniformity of Through-Mask electroplated Ni thin-film 透掩膜镀镍薄膜不均匀性的研究

2008 International Conference on Electronic Packaging Technology & High Density Packaging Pub Date : 2008-07-28 DOI: 10.1109/ICEPT.2008.4606993

Jun Tang, Hong Wang, Rui Liu, Shengping Mao, Xiaolin Zhao, G. Ding

{"title":"Study on non-uniformity of Through-Mask electroplated Ni thin-film","authors":"Jun Tang, Hong Wang, Rui Liu, Shengping Mao, Xiaolin Zhao, G. Ding","doi":"10.1109/ICEPT.2008.4606993","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4606993","url":null,"abstract":"Through-mask electroplating has been widely used in the fabrication of chips, BGA substrates and PCBs etc. The uniformity of plating thin-film is the major factor contributed to the reliability of the products. Currently, it is usually by setting optimum plating parameters and adopting electrochemical method to achieve the uniformity of plating. However, the problem of non-uniform distribution of electric field, which is the major cause of the non-uniformity of the plating thin-film, has not been solved. In this paper, finite element method (FEM) was developed to analyze the non-uniform distribution of electric field under different conditions in the process of electroplating. The results show that different thickness of photo-resist and size of electroplating cell are two major factors contribute to the uniformity of plating thin-film. The uniform of electroplating cell can be improved by adding in-chip auxiliary electrode. Also better uniformity of the plating film in radial direction can achieved by setting a shield in the proper position of the plating solution and annular out-chip auxiliary electrode (Cu) around the wafer. The simulation results were consistent with experimental results, which proved that finite element method is an effect way to simulate the electroplating process.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":"162 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78071201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Electrodeposition of palladium films on Ni-Co coatings Ni-Co镀层上钯膜的电沉积

2008 International Conference on Electronic Packaging Technology & High Density Packaging Pub Date : 2008-07-28 DOI: 10.1109/ICEPT.2008.4607048

Yanping He, D. Ding, Xiang Gao, Z. Chen, Ming Li, D. Mao

引用次数: 0

Mold array package for POP applications 用于POP应用的模具阵列包

2008 International Conference on Electronic Packaging Technology & High Density Packaging Pub Date : 2008-07-28 DOI: 10.1109/ICEPT.2008.4606938

A. Lee, Louie Huang, M. Hung

{"title":"Mold array package for POP applications","authors":"A. Lee, Louie Huang, M. Hung","doi":"10.1109/ICEPT.2008.4606938","DOIUrl":"https://doi.org/10.1109/ICEPT.2008.4606938","url":null,"abstract":"The package on package (POP) stacking is getting more and more popular for system in package (SIP) applications. But during the assembly process, the POP had encountered the challenge of packages stacking yield loss, especially when top package and bottom package stacking. The key factors are the mount height of top package, the mold cap of bottom package, and the metallized ball land on the top surface of bottom package. JEDEC JC-11 has defined the rules of two packages stacking. However, the fine pitch package stacking application will meet the process capability limitation, including thinner mold cap, wafer thinning and the lowest wire bond loop height challenges. The POP used the top gate mold chase for the bottom package to expose the metallized ball land on the top side of package which is a dedicated molding tooling. Also, some process are used for solving yield loss issues such as a POP with interposer between top package and bottom package, or a bottom package with pre-mounted the solder ball on chip side ready for top package to attach. Those are customized tooling and not a prevailing tooling that increases the developing cost and timing. To resolve the stacking process yield loss issue, a MAPPOP solution had been revealed for eliminating the limitation between the top and bottom package stacking. The assembly process of mold array package (MAP) for fine pitch BGA has been implemented for MAPPOP applications. In the paper, the package design rules, and assembly process of exposed metallized ball land on the top surface of bottom package had been discussed. Finally the warpage performance and the packaging level reliability had also been discussed and analyzed.","PeriodicalId":6324,"journal":{"name":"2008 International Conference on Electronic Packaging Technology & High Density Packaging","volume":"50 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2008-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75741070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

High-Q on-chip inductors embedded in wafer-level package for RFIC applications 用于RFIC应用的高q级片上电感器嵌入晶圆级封装

2008 International Conference on Electronic Packaging Technology & High Density Packaging Pub Date : 2008-07-28 DOI: 10.1109/ICEPT.2008.4606957

Tao Feng, Jian Cai, Hye-Kyong Kwon, Qian Wang, Xinyu Dou

引用次数: 1