Parametric study on board-level electronic test device subjected to JEDEC vibration loads

Chang-Lin Yeh, Y. Lai, Ching-Chun Wang
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引用次数: 3

Abstract

We derive in this paper equations of motion of board-level IC packages subjected to swept sine vibration loads following the support excitation scheme. Harmonic analysis is performed based on the argument such that at each loading state over the swept sine process, hysteresis responses of solder joints following the isotropic hardening rule vanish fairly quickly so that plasticity is fully developed. Computed and measured acceleration response spectra of a board-level test vehicle are benchmarked. Stress-based failure indices as well as elastoplastic responses and strain rates of solder joints are examined for the test vehicle subjected to swept sine vibration tests of different acceleration levels with vibration frequencies up to 2 kHz.
JEDEC振动载荷下板级电子测试装置的参数化研究
本文推导了支撑激励方案下板级集成电路封装在扫频正弦振动载荷作用下的运动方程。谐波分析基于这样的论点:在扫频正弦过程的每个加载状态下,遵循各向同性硬化规则的焊点的滞后响应消失得相当快,从而使塑性得到充分发展。对一台板级试验车的计算和实测加速度响应谱进行了基准测试。在振动频率高达2khz的不同加速度水平下,对试验车辆的应力失效指标、焊点弹塑性响应和应变率进行了测试。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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