Journal of Computational Electronics最新文献

Synergistic alteration of end-capped groups into central core fused perylene-based materials to boost their photovoltaic properties 端帽基团协同改变为中心核心熔融苝基材料，以提高其光伏性能

IF 2.5 4区工程技术

Journal of Computational Electronics Pub Date : 2025-10-04 DOI: 10.1007/s10825-025-02427-x

Mashal Khan, Laiba Amir, Sadia Jamal, Faiz Rasool, Tansir Ahamad, Nayab Tahir

{"title":"Synergistic alteration of end-capped groups into central core fused perylene-based materials to boost their photovoltaic properties","authors":"Mashal Khan, Laiba Amir, Sadia Jamal, Faiz Rasool, Tansir Ahamad, Nayab Tahir","doi":"10.1007/s10825-025-02427-x","DOIUrl":"10.1007/s10825-025-02427-x","url":null,"abstract":"<div>Non-fullerene organic chromophores are widely used in photovoltaic materials. In this study, the perylene-based molecules (PBI1-PBI8) with an A–π–A framework were designed by modifying the terminal acceptor of the reference compound (PBIR). Density functional theory (DFT) and time-dependent DFT (TD-DFT) calculations at the M06/6-311G(d,p) level were employed to optimize and verify their true minima structures. Further, the optimized structures were used for investigating the frontier molecular orbitals (FMOs), transition density matrix (TDM), density of states (DOS), open-circuit voltage (Voc), and binding energy (Eb) to understand their optoelectronic and photovoltaic performances. The HOMO–LUMO energy gap of PBI1-PBI8 was obtained in a range of 2.546–2.610 eV, comparable to the PBIR reference (2.553 eV). Additionally, they showed wide absorption spectra as 571.540–599.972 nm in the gas phase and 598.871–615.031 nm in the chloroform solvent phase. The designed derivatives also exhibited lower binding energies (0.436–0.482 eV). All the new chromophores (PBI1-PBI8) showed a reasonable improvement in photovoltaic response as shown by their prominent open-circuit voltages. These results suggest that the novel perylene-based chromophores may be suitable candidates for highly efficient photovoltaic materials.</div>","PeriodicalId":620,"journal":{"name":"Journal of Computational Electronics","volume":"24 6","pages":""},"PeriodicalIF":2.5,"publicationDate":"2025-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145210626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Analysis of a micromachined vibrating beam accelerometer for early earthquake warning system 用于地震早期预警系统的微机械振动梁加速度计分析

IF 2.5 4区工程技术

Journal of Computational Electronics Pub Date : 2025-10-04 DOI: 10.1007/s10825-025-02420-4

Mrinmoy Singha, Reshmi Maity, Niladri Pratap Maity

引用次数: 0

Time-domain response improvement and bandwidth expansion of graphene nanoribbon interconnects using two types of high-k dielectric materials 使用两种高k介电材料的石墨烯纳米带互连的时域响应改善和带宽扩展

IF 2.5 4区工程技术

Journal of Computational Electronics Pub Date : 2025-10-03 DOI: 10.1007/s10825-025-02433-z

Yuqi Wu, Zhongliang Pan

{"title":"Time-domain response improvement and bandwidth expansion of graphene nanoribbon interconnects using two types of high-k dielectric materials","authors":"Yuqi Wu, Zhongliang Pan","doi":"10.1007/s10825-025-02433-z","DOIUrl":"10.1007/s10825-025-02433-z","url":null,"abstract":"<div>With the continued scaling of integrated circuit (IC) technology nodes, optimizing interconnect performance has become critical for improving overall system performance. To overcome the limitations of single high-k dielectric insertions, we introduce a dual-dielectric approach using two distinct high-k materials within multilayer graphene nanoribbon (MLGNR) interconnects. This strategy improves carrier mobility and suppresses interfacial scattering, thereby enhancing interconnect signal transmission. The paper develops a comprehensive model that incorporates equivalent resistance, capacitance, and inductance. Based on the model, this paper applies the ABCD parameter matrix method to derive the interconnect transfer function and clarify how the dual-dielectric configuration enhances signal propagation, expands bandwidth, and reduces delay. Theoretical derivations are used to evaluate the proposed structure’s impact on key performance indicators, including mean free path (MFP), scattering resistance, delay, gain, 3 dB bandwidth, and energy-delay product (EDP). The results demonstrate that, compared to single-dielectric designs, the dual-dielectric strategy generally improves performance by reducing settling time and expanding the 3 dB bandwidth, leading to significant overall enhancements in signal transmission and efficiency. This paper provides theoretical support and data evidence for multi-dielectric design strategies in nanoscale MLGNR interconnect structures.</div>","PeriodicalId":620,"journal":{"name":"Journal of Computational Electronics","volume":"24 6","pages":""},"PeriodicalIF":2.5,"publicationDate":"2025-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://link.springer.com/content/pdf/10.1007/s10825-025-02433-z.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145210358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A novel linear memristor model for data storage and synaptic applications 一种用于数据存储和突触应用的新型线性忆阻器模型

IF 2.5 4区工程技术

Journal of Computational Electronics Pub Date : 2025-10-02 DOI: 10.1007/s10825-025-02438-8

Nishant Ranjan, Chandra Prakash Singh, Harsh Ranjan, Vivek Pratap Singh, Saurabh Kumar Pandey

引用次数: 0

Optimum design of a lateral superjunction considering charge imbalance due to process variations 考虑工艺变化引起的电荷不平衡的横向超结优化设计

IF 2.5 4区工程技术

Journal of Computational Electronics Pub Date : 2025-10-01 DOI: 10.1007/s10825-025-02432-0

Rachita Mohapatra, K. Akshay

{"title":"Optimum design of a lateral superjunction considering charge imbalance due to process variations","authors":"Rachita Mohapatra, K. Akshay","doi":"10.1007/s10825-025-02432-0","DOIUrl":"10.1007/s10825-025-02432-0","url":null,"abstract":"<div>Lateral superjunctions (LSJ) are potential candidates for CMOS compatible high voltage devices in next-generation power integrated circuits. The prior works have modeled and developed design guidelines only for an ideal balanced LSJ, i.e., having equal charge in the n- and p-pillars. However, inevitable process variation during fabrication results in charge imbalance, ({k_{N}}), that yields a breakdown voltage, ({V_textrm{BR}}), significantly lower than the target breakdown voltage, ({V_textrm{BR,target}}). In this work, we use the method of Lagrange multipliers to derive analytical equations for the optimum pillar parameters of an LSJ; these parameters yield the minimum specific ON-resistance, ({R_textrm{ONSP}}), for a ({V_textrm{BR,target}}) and ({k_{N}}). The analytical solutions are verified using well-calibrated TCAD simulations for 0.1–1 kV Si LSJs and 1–10 kV 4H-SiC LSJs for ({k_{N}}) from 0.05 to 0.30 (signifying 5 to 30% imbalance between the n- and p-pillar charge). Our solutions show that the optimum aspect ratio, ({r_{0}}), varies between 8–12 for Si LSJs and 10–15 for 4H-SiC LSJs. Notably, our solution for an LSJ is found to yield significantly different optimum pillar parameters than our earlier solution for a vertical SJ for the same ({V_textrm{BR}}) and ({k_{N}}), due to the difference in their dependency of ({R_textrm{ONSP}}) on the pillar parameters. This justifies the need for customized solution for the design of LSJ.</div>","PeriodicalId":620,"journal":{"name":"Journal of Computational Electronics","volume":"24 6","pages":""},"PeriodicalIF":2.5,"publicationDate":"2025-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145210750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Gazeau-Klauder coherent states for a harmonic position-dependent mass 调和位置相关质量的加泽-克劳德相干态

IF 2.5 4区工程技术

Journal of Computational Electronics Pub Date : 2025-09-30 DOI: 10.1007/s10825-025-02431-1

Daniel Sabi Takou, Assimiou Yarou Mora, Ibrahim Nonkané, Latévi M. Lawson, Gabriel Y. H. Avossevou

引用次数: 0

Enhancing memory performance in IGZO-based 2T0C DRAM through comparative analysis of CAA and GAA FET structures 通过对CAA和GAA FET结构的比较分析，提高基于igzo的2T0C DRAM的存储性能

IF 2.5 4区工程技术

Journal of Computational Electronics Pub Date : 2025-09-30 DOI: 10.1007/s10825-025-02429-9

Minseop Kim, Joonhyeok Lee, Hyunbo Cho, Jongwook Jeon

{"title":"Enhancing memory performance in IGZO-based 2T0C DRAM through comparative analysis of CAA and GAA FET structures","authors":"Minseop Kim, Joonhyeok Lee, Hyunbo Cho, Jongwook Jeon","doi":"10.1007/s10825-025-02429-9","DOIUrl":"10.1007/s10825-025-02429-9","url":null,"abstract":"<div>As digital technology advances, the demand for high-performance, high-density, and low-power memory technologies continues to grow. To address these needs, the 2 Transistor 0 Capacitor (2T0C) DRAM architecture, featuring nondestructive read operations, has emerged as a promising alternative to conventional 1 Transistor 1 Capacitor DRAM. The InGaZnO (IGZO) channel material, known for low off-current and high mobility, enables long data retention and enhanced power efficiency in 2T0C DRAM. In this study, IGZO-based channel-all-around (CAA) and gate-all-around (GAA) FET structures were implemented using TCAD simulations, which were based on the well-calibrated physical carrier transport models with the measured IGZO channel device. The electrical characteristics, including the on/off-current ratio (Ion/Ioff), were compared at the single-transistor level. For the 2T0C DRAM cell, variations in the gate length, critical dimension (CD), and underlap structure of the writing transistor (WTR) and reading transistor (RTR) were investigated, to evaluate memory characteristics such as data writing speed, retention, and single-cell disturbance, along with the feasibility of multi-bit operation. The analysis showed that the CAA structure provides faster data writing speeds, whereas the GAA structure—especially in the WTR configuration and 3 × 3 array design—offers significantly better retention and single-cell disturbance immunity. This study provides clear guidance for the structural optimization of IGZO-based 2T0C DRAM and practical insights into the designing next-generation high-density memory technologies.</div>","PeriodicalId":620,"journal":{"name":"Journal of Computational Electronics","volume":"24 6","pages":""},"PeriodicalIF":2.5,"publicationDate":"2025-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145210955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Influence of passivation, doping and geometrical parameters on the avalanche breakdown of GaN SBDs 钝化、掺杂和几何参数对GaN sdd雪崩击穿的影响

IF 2.5 4区工程技术

Journal of Computational Electronics Pub Date : 2025-09-27 DOI: 10.1007/s10825-025-02430-2

B. Orfao, R. A. Peña, B. G. Vasallo, S. Pérez, J. Mateos, T. González

{"title":"Influence of passivation, doping and geometrical parameters on the avalanche breakdown of GaN SBDs","authors":"B. Orfao, R. A. Peña, B. G. Vasallo, S. Pérez, J. Mateos, T. González","doi":"10.1007/s10825-025-02430-2","DOIUrl":"10.1007/s10825-025-02430-2","url":null,"abstract":"<div>The breakdown of GaN-based Schottky barrier diodes associated with impact ionization events initiated by electrons injected by tunneling is physically analyzed by means of a Monte Carlo simulator self-consistently coupled with a two-dimensional solution of the Poisson equation. Simulations of a realistic topology where different geometrical parameters are modified allow to identify their influence on the breakdown voltage. The correct physical modeling of two-dimensional effects is essential for a proper prediction of the breakdown. Epilayer doping and thickness, dielectric used for the passivation and lateral extension of the epilayer are analyzed. As expected, the lower the doping and the thicker the epilayer, the higher the value found for the breakdown voltage, but, interestingly, the results also indicate that the peak electric field present at the edge of the Schottky contact, which may be reduced by means of high-k dielectric passivation and a short lateral extension of the epilayer, plays a key role in the breakdown.</div>","PeriodicalId":620,"journal":{"name":"Journal of Computational Electronics","volume":"24 6","pages":""},"PeriodicalIF":2.5,"publicationDate":"2025-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://link.springer.com/content/pdf/10.1007/s10825-025-02430-2.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145170678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Quantum gate synthesis by small perturbation of a particle in a box with electric field 有电场的盒子中粒子的微扰合成量子门

IF 2.5 4区工程技术

Journal of Computational Electronics Pub Date : 2025-09-25 DOI: 10.1007/s10825-025-02425-z

Kumar Gautam

{"title":"Quantum gate synthesis by small perturbation of a particle in a box with electric field","authors":"Kumar Gautam","doi":"10.1007/s10825-025-02425-z","DOIUrl":"10.1007/s10825-025-02425-z","url":null,"abstract":"<div>A quantum unitary gate is studied theoretically by perturbing a free charged particle in a one-dimensional box with a time- and position-varying electric field. The perturbed Hamiltonian is composed of a free particle Hamiltonian plus a perturbing electric potential such that the Schrödinger evolution in time T, the unitary evolution operator of the unperturbed system after truncation to a finite number of energy levels, approximates a given unitary gate such as the quantum Fourier transform gate. The idea is to truncate the half-wave Fourier sine series to M terms in the spatial variable (textbf{x}) before extending the potential as a Dyson series in the interaction picture to compute the evolution operator matrix elements up to the linear and quadratic integral functionals of ( textbf{V}_n(t)^{prime})s. As a result, we used the Dyson series with the Frobenius norm to reduce the difference between the derived gate energy and the given gate energy, and we determined the temporal performance criterion by plotting the noise-to-signal energy ratio. A mathematical explanation for a quantum gate’s magnetic control has also been provided. In addition, we provide a mathematical explanation for a quantum gate that uses magnetic control.</div>","PeriodicalId":620,"journal":{"name":"Journal of Computational Electronics","volume":"24 6","pages":""},"PeriodicalIF":2.5,"publicationDate":"2025-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145170245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design of a novel memtranstor emulator using CCIIs and experimental validation 基于CCIIs的新型忆阻晶体管仿真器的设计与实验验证

IF 2.5 4区工程技术

Journal of Computational Electronics Pub Date : 2025-09-25 DOI: 10.1007/s10825-025-02424-0

Muzaffer Çayır, Mehmet Sağbaş

{"title":"Design of a novel memtranstor emulator using CCIIs and experimental validation","authors":"Muzaffer Çayır, Mehmet Sağbaş","doi":"10.1007/s10825-025-02424-0","DOIUrl":"10.1007/s10825-025-02424-0","url":null,"abstract":"<div>This study introduces a new memtranstor emulator circuit using second-generation current conveyors (CCII), providing an alternative to the only existing memtranstor emulator circuit in the literature. The proposed circuit consists of three CCIIs, one analog multiplier (AD633), two grounded resistors, and three grounded capacitors. The design is implemented using 180 nm CMOS technology, and its functionality is validated through PSPICE simulations. The circuit’s behavior is analyzed under various conditions including pinched hysteresis loops, Monte Carlo analysis, memory effect simulations, and temperature variation tests, all of which confirm its proper operation. Additionally, the circuit can be easily adapted between incremental and decremental memory emulators, demonstrating its versatility for various applications. The proposed emulator has been further validated through experimental implementation, confirming its feasibility for practical applications. A memtranstor-based chaotic oscillator is presented as an application example. Compared to the existing design in the literature, the proposed emulator offers several key advantages: It employs fewer active and passive components, leading to a simpler structure with the potential for more compact implementation. The absence of operational amplifiers (op-amps) improves bandwidth performance by eliminating the fixed gain-bandwidth product limitation, enabling higher gain levels at broader bandwidths. Additionally, the use of low-power CMOS parameters potentially allows for lower supply voltages, which, along with fewer components, can significantly reduce power consumption.</div>","PeriodicalId":620,"journal":{"name":"Journal of Computational Electronics","volume":"24 6","pages":""},"PeriodicalIF":2.5,"publicationDate":"2025-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145169173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0