Modelling and analysis of a negative capacitance junctionless FinFET with ferroelectric spacer: a paradigm shift in low power electronics

This article proposes an analytical model for the threshold voltage of a negative capacitance junctionless FinFET (NC-JL FinFET) with ferroelectric spacer. In the proposed study the new concept of ferroelectric as a gate dielectric as well as spacer is introduced with a NC-JL FinFET as a noteworthy development in the field of low-power electronics. The effect of fringing field due to the source/drain ferroelectric spacer on the potential distribution function and threshold voltage has been taken into consideration. The effect of the ferroelectric as a spacer on the surface potential and threshold voltage for a NC-JL FinFET is analysed and compared with a dielectric as the spacer. The results of the proposed models are also validated and compared with simulated results of Sentaurus TCAD device simulator. Further we have compared the ON and OFF current, ION/IOFF ratio, Subthreshold Slope (SS) etc. of the ferroelectric and dielectric as spacer for the NC-JL FinFET. Furthermore, its performance has been analysed for different spacer lengths, Fin thickness and spacer length.