IEEE Transactions on Electronics Packaging Manufacturing最新文献

{"title":"A Neural-Network Approach for Defect Recognition in TFT-LCD Photolithography Process","authors":"Li-Fei Chen, Chao-Ton Su, Mengyu Chen","doi":"10.1109/TEPM.2008.926117","DOIUrl":"https://doi.org/10.1109/TEPM.2008.926117","url":null,"abstract":"Since the advent of high qualification and tiny technology, yield control in the photolithography process has played an important role in the manufacture of thin-film transistor-liquid crystal displays (TFT-LCDs). Through an auto optic inspection (AOI), defect points from the panels are collected, and the defect images are generated after the photolithography process. The defect images are usually identified by experienced engineers or operators. Evidently, human identification may produce potential misjudgments and cause time loss. This study therefore proposes a neural-network approach for defect recognition in the TFT-LCD photolithography process. There were four neural-network methods adopted for this purpose, namely, backpropagation, radial basis function, learning vector quantization 1, and learning vector quantization 2. A comparison of the performance of these four types of neural-networks was illustrated. The results showed that the proposed approach can effectively recognize the defect images in the photolithography process.","PeriodicalId":55010,"journal":{"name":"IEEE Transactions on Electronics Packaging Manufacturing","volume":"25 1","pages":"1-8"},"PeriodicalIF":0.0,"publicationDate":"2009-01-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89257459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Application of a Genetic Algorithm to the Design Optimization of a Multilayer Probe Card for Wafer-Level Testing","authors":"De-Shin Liu, M. Shih, Chi-Ming Chang","doi":"10.1109/TEPM.2008.2010776","DOIUrl":"https://doi.org/10.1109/TEPM.2008.2010776","url":null,"abstract":"The number of input and output pads on high-performance IC devices has increased in recent years, and hence wafer-level testing is conventionally performed using a probe card with a multilayer needle layout. This paper employs ANSYS commercial software and a Genetic Algorithm (GA) to optimize the design parameters of a multilayer needle probe card such that the scrub marks produced by the different needle layers are of approximately equal length. A dummy probe card containing both a conventional multilayer needle layout and the optimized needle layout is then fabricated and used in a series of single-contact probing tests. The results reveal that the scrub marks produced by the optimized needle layout are both shorter and of a more uniform length that those produced by the conventional needle design. For both needle layouts, a lower and more stable contact resistance is obtained as the overdrive distance is increased. Finally, a multicontact probing test is performed to evaluate the effect on the contact resistance of probe tip contamination following repeated surface contacts. The results show that the needles in the optimized layout are less heavily contaminated than those in the conventional layout, and hence the contact resistance is both lower and more stable. As a consequence, the probe card requires cleaning less frequently and hence its service life is improved.","PeriodicalId":55010,"journal":{"name":"IEEE Transactions on Electronics Packaging Manufacturing","volume":"77 1","pages":"49-58"},"PeriodicalIF":0.0,"publicationDate":"2009-01-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89863108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design of Experiments for Board-Level Solder Joint Reliability of PBGA Package Under Various Manufacturing and Multiple Environmental Loading Conditions","authors":"Haiyu Qi, M. Osterman, M. Pecht","doi":"10.1109/TEPM.2008.2005905","DOIUrl":"https://doi.org/10.1109/TEPM.2008.2005905","url":null,"abstract":"A design of experiments was conducted to determine the reliability of plastic ball grid array packages under various manufacturing and multiple environmental loading conditions. Parameters included conformal coating methods, underfill, solder mask defined, and non-solder mask defined pads. Board-level temperature cycling, vibration, and combined temperature cycling and vibration testing were performed to quantify the reliability and identify preferred design parameters. Through the main effects and interaction analysis, test results show underfill is the key parameter related to the solder joint reliability improvement. Conformal coat method and printed circuit board pad design are not main effects on solder joint reliability. No interactive relationship exists among these three factors under temperature cycling loading, but some interactive relationship between printed circuit board pad type and the conformal coating method exists under vibration and combined loading conditions.","PeriodicalId":55010,"journal":{"name":"IEEE Transactions on Electronics Packaging Manufacturing","volume":"89 5 1","pages":"32-40"},"PeriodicalIF":0.0,"publicationDate":"2009-01-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82791468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Flip Chip Bonding of 68 $times$ 68 MWIR LED Arrays","authors":"N. Das, M. Taysing-Lara, K. Olver, F. Kiamilev, J. Prineas, J. Olesberg, E. Koerperick, L. M. Murray, T. Boggess","doi":"10.1109/TEPM.2008.2005062","DOIUrl":"https://doi.org/10.1109/TEPM.2008.2005062","url":null,"abstract":"The flip chip bonding process is optimized by varying the bonding pressure, temperature, and time. The 68times68 mid wave infrared (MWIR) LED array was hybridized onto Si-CMOS driver array with same number of pixels. Each pixel has two indium bumps, one for cathode and another for anode. Both LED array and CMOS drivers have 15-mum-square Indium bump contact pads. We used Karl Suss FC150 flip chip machine for bonding of CMOS driver array onto LED array. From the LED current-voltage characteristics, it is concluded that the optimized flip chip bonding process results in uniform contact and very low contact resistance. Both electrical and optical characteristics of LED array after flip chip bonding are presented.","PeriodicalId":55010,"journal":{"name":"IEEE Transactions on Electronics Packaging Manufacturing","volume":"44 1","pages":"9-13"},"PeriodicalIF":0.0,"publicationDate":"2009-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85778057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Coupled Power and Thermal Cycling Reliability of Board-Level Package-on-Package Stacking Assembly","authors":"T. Wang, Y. Lai, Chang-Chi Lee, Yu-Cheng Lin","doi":"10.1109/TEPM.2008.2005300","DOIUrl":"https://doi.org/10.1109/TEPM.2008.2005300","url":null,"abstract":"In this paper, the sequential thermal-mechanical coupling analysis, which solves in turn the transient temperature field and subsequent thermomechanical deformations, is performed to investigate thermal characteristics along with fatigue reliability of a board-level package-on-package (PoP) stacking assembly under coupled power and thermal cycling test conditions. Effects of powering sequences on thermal characteristics and fatigue reliability of the PoP are examined. The numerical analysis shows that coupled power and thermal cycling creates temperature excursions based on the thermal cycling profile. Also, reliability of the PoP is highly related to the range of temperature excursions and the degree of deviation of the temperature profile from the thermal cycling profile.","PeriodicalId":55010,"journal":{"name":"IEEE Transactions on Electronics Packaging Manufacturing","volume":"1 1","pages":"14-21"},"PeriodicalIF":0.0,"publicationDate":"2009-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78243929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Void Formation Study of Flip Chip in Package Using No-Flow Underfill","authors":"S. Lee, M. Yim, R. Master, C. Wong, D. Baldwin","doi":"10.1109/TEPM.2008.2002951","DOIUrl":"https://doi.org/10.1109/TEPM.2008.2002951","url":null,"abstract":"The advanced flip chip in package (FCIP) process using no-flow underfill material for high I/O density and fine-pitch interconnect applications presents challenges for an assembly process that must achieve high electrical interconnect yield and high reliability performance. With respect to high reliability, the voids formed in the underfill between solder bumps or inside the solder bumps during the no-flow underfill assembly process of FCIP devices have been typically considered one of the critical concerns affecting assembly yield and reliability performance. In this paper, the plausible causes of underfill void formation in FCIP using no-flow underfill were investigated through systematic experimentation with different types of test vehicles. For instance, the effects of process conditions, material properties, and chemical reaction between the solder bumps and no-flow underfill materials on the void formation behaviors were investigated in advanced FCIP assemblies. In this investigation, the chemical reaction between solder and underfill during the solder wetting and underfill cure process has been found to be one of the most significant factors for void formation in high I/O and fine-pitch FCIP assembly using no-flow underfill materials.","PeriodicalId":55010,"journal":{"name":"IEEE Transactions on Electronics Packaging Manufacturing","volume":"61 1","pages":"297-305"},"PeriodicalIF":0.0,"publicationDate":"2008-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80995637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Automatic Microassembly Using Visual Servo Control","authors":"Lidai Wang, J. Mills, W. Cleghorn","doi":"10.1109/TEPM.2008.926118","DOIUrl":"https://doi.org/10.1109/TEPM.2008.926118","url":null,"abstract":"We propose an automatic microassembly method that can be used to construct three-dimensional microelectromechanical system (MEMS) structures. A six degree-of-freedom micromanipulator, equipped with a passive microgripper, is employed to grasp, manipulate, and join the micropart using visual feedback from an optical microscope. The proposed process utilizes a two-stage alignment strategy to perform the micro-grasping and micro-joining tasks. Using a vision-based localization method, the Cartesian coordinates of the manipulated micropart in three-dimensional space are determined. Further, a vision-based contact sensor determines the contact state between two micro-components in three dimensions to facilitating the micro-joining tasks. Visual servo control is used for accurate position feedback in three Cartesian coordinates during microassembly tasks. The necessary steps towards construction of complex three-dimensional MEMS devices, i.e., grasping a micropart, manipulating it, joining it to another micropart, and finally releasing it from the microgripper, have been successfully carried out using a six degree-of-freedom micromanipulator. Experiments demonstrate both the efficiency and validity of the proposed automatic assembly approach.","PeriodicalId":55010,"journal":{"name":"IEEE Transactions on Electronics Packaging Manufacturing","volume":"43 1","pages":"316-325"},"PeriodicalIF":0.0,"publicationDate":"2008-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85610547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Bondability Study of Chip-on-Film (COF) Inner Lead Bonding (ILB) Using Conventional Gang Bonder","authors":"Ching-I Chen, C. Ni, Chi-Min Chang, Shao-Chiun Wu, De-Shin Liu","doi":"10.1109/TEPM.2008.2002025","DOIUrl":"https://doi.org/10.1109/TEPM.2008.2002025","url":null,"abstract":"Inner lead bonding (ILB) is used to thermomechanically join the Cu inner leads on a flexible film tape and Au bumps on a driver IC chip to form electrical paths. With the newly developed film carrier assembly technology, called chip on film (COF), the bumps are prepared separately on a film tape substrate and bonded on the finger lead ends beforehand; therefore, the assembly of IC chips can be made much simpler and cheaper. In this paper, three kinds of COF samples, namely forming, wrinkle, and flat samples, were prepared using conventional gang bonder. The peeling test was used to examine the bondability of ILB in terms of the adhesion strength between the inner leads and the bumps. According to the peeling test results, flat samples have competent strength, less variation, and better appearance than when using flip-chip bonder.","PeriodicalId":55010,"journal":{"name":"IEEE Transactions on Electronics Packaging Manufacturing","volume":"127 1","pages":"285-290"},"PeriodicalIF":0.0,"publicationDate":"2008-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75813878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"3-D Measurement of Solder Paste Using Two-Step Phase Shift Profilometry","authors":"Tak-Wai Hui, G. Pang","doi":"10.1109/TEPM.2008.2004573","DOIUrl":"https://doi.org/10.1109/TEPM.2008.2004573","url":null,"abstract":"A two-step phase shift profilometry method (2-step PSP) with prefiltering and postfiltering stages is proposed to reconstruct the 3-D profile of solder paste. Two sinusoidal patterns which are pi-out-of-phase are used in the 3-D reconstruction. The new method uses only two fringe patterns rather than four as the four-step phase shift profilometry (4-step PSP). In Fourier transform profilometry (FTP), a bandpass filter is required to extract the fundamental spectrum from the background and higher order harmonics due to camera noise and imperfectness of the pattern projector. By using two pi-out-of-phase sinusoidal fringe patterns, the background term can be eliminated directly by taking the average of the two fringe patterns. The fringe pattern which is close to its ideal form can also be recovered from the averaging process. Prefiltering is utilized in filtering raw images to remove noise causing higher order harmonics. Hilbert transform is then used to obtain the in-quadrature component of the processed fringe pattern. Postfiltering is applied for reconstructing an appropriate 3-D profile.","PeriodicalId":55010,"journal":{"name":"IEEE Transactions on Electronics Packaging Manufacturing","volume":"72 4 1","pages":"306-315"},"PeriodicalIF":0.0,"publicationDate":"2008-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87747925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermomechanical Reliability of Nickel Pillar Interconnections Replacing Flip-Chip Solder Without Underfill","authors":"A. Aggarwal, P. Raj, B. Lee, M. Yim, M. Iyer, C. Wong, R. Tummala","doi":"10.1109/TEPM.2008.2001974","DOIUrl":"https://doi.org/10.1109/TEPM.2008.2001974","url":null,"abstract":"Interconnect technologies between ICs and packages or boards have a significant impact on the IC performance and packaging density. Today, the interconnections are typically accomplished with either wire bonding or flip-chip solders. While both of these technologies are incremental, they also run into either electrical or mechanical barriers as they are extended to higher density of interconnections. Downscaling traditional solder bump interconnect might not satisfy the thermomechanical reliability requirements at very fine-pitches. Alternate interconnection approaches such as compliant interconnects typically require lengthy connections and are therefore limited in terms of electrical properties, although expected to meet the mechanical requirements. This paper reports fine-pitch interconnection technologies using nano-structured nickel as primary interconnection material. The nano-grained nickels are produced by electroplating process. The primary nano-structured interconnects are assembled with different bonding methods to provide organic compatible low-temperature fabrication. Au-Sn and Sn-Cu are used for solder-based assembly of nano-nickel interconnections. Low modulus anisotropic conductive films (ACFs) are also used as an alternate bonding route of the solders. No underfilling is used in all the interconnect structures evaluated in this paper. Assembly are accomplished on different coefficient of thermal expansion (CTE) substrates including FR-4 with 18 ppm/degC, advanced organic substrates with 10 ppm/degC, novel low CTE (3 ppm/degC) substrates based on carbon-silicon carbide (C-SiC). The thermomechanical reliability of all the nano-interconnects assembled on different CTE substrates with different bonding approaches is evaluated by thermal shock testing and finite-element analysis. Nano-nickel interconnects bonded with the ACF showed the highest reliability withstanding 1500 cycles. In all cases, no apparent failure was observed in the primary nano-nickel metal interconnects. This technology is expected to be easily downscaled to submicrometer and nano-scale unlike the current solder technologies leading to true nano-interconnections.","PeriodicalId":55010,"journal":{"name":"IEEE Transactions on Electronics Packaging Manufacturing","volume":"2 1","pages":"341-354"},"PeriodicalIF":0.0,"publicationDate":"2008-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74597463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}