IEEE Transactions on Electronics Packaging Manufacturing最新文献_第6页

Wafer-Level Package With Simultaneous TSV Connection and Cavity Hermetic Sealing by Solder Bonding for MEMS Device MEMS器件的晶圆级封装，同时采用TSV连接和焊接腔密封

IEEE Transactions on Electronics Packaging Manufacturing Pub Date : 2009-05-29 DOI: 10.1109/TEPM.2009.2021766

Yuhan Cao, Wenguo Ning, L. Luo

引用次数: 40

Modeling of the Fluid Volume Transferred in Contact Dispensing Processes 接触点胶过程中流体体积传递的建模

IEEE Transactions on Electronics Packaging Manufacturing Pub Date : 2009-05-29 DOI: 10.1109/TEPM.2009.2020515

X.B. Chen, M. G. Li, N. Cao

引用次数: 16

Concurrent Optimization of Crescent Bond Pull Force and Tail Breaking Force in a Thermosonic Cu Wire Bonding Process 热超声铜丝键合过程中月牙键拉力和断尾力的同步优化

IEEE Transactions on Electronics Packaging Manufacturing Pub Date : 2009-05-29 DOI: 10.1109/TEPM.2009.2019338

J. Lee, M. Mayer, Y. Zhou, S. Hong, J. Moon

{"title":"Concurrent Optimization of Crescent Bond Pull Force and Tail Breaking Force in a Thermosonic Cu Wire Bonding Process","authors":"J. Lee, M. Mayer, Y. Zhou, S. Hong, J. Moon","doi":"10.1109/TEPM.2009.2019338","DOIUrl":"https://doi.org/10.1109/TEPM.2009.2019338","url":null,"abstract":"In conventional wire bonding process optimization, the crescent bond is tested by destructive pulling the loop and measure the pull force (PF) required to break the bond. While this method assures the final quality, it does not necessarily minimize production stoppages which can reduce throughput significantly. Many stoppages are caused by short-tail and tail-lift errors which in turn are caused by reduced tail bond strength. The tail breaking force (TBF) is a measure for tail bond strength. A consistent tail breaking operation is needed for robust Cu wire bond production with little operator assistance required to restart stopped machines. We report the concurrent (simultaneous) optimization of PF and TBF using standard pull testing and a method that directly measures the tail bond strength in-process, respectively. The example process uses standard 25-mum-diameter Cu wire on standard Ag-plated leadframe diepads and wire loops oriented perpendicular to the ultrasonic horn. The optimization consists of (1) finding the factors to obtain a symmetrical bond shape, (2) choosing fixed values for bond time (25 ms) and heater stage temperature (220degC), and (3) adding the new optimization step of maximizing the TBF by iteratively optimizing the impact force (IF), bonding force (BF), and ultrasound (US) parameters. Among these parameters, the US and BF are the most significant. A process window (PW) is defined as the set of US/BF parameter combinations that result in a response being inside a previously defined range. PWs for PF and TBF are determined and compared with each other. There is only a partial overlap of these PWs. To increase the process capability index (cpk) for TBF, it is recommended to first carry out conventional PF optimization followed by a minimization of the bonding force parameter to the lowest value still fulfilling the PF cpk requirement.","PeriodicalId":55010,"journal":{"name":"IEEE Transactions on Electronics Packaging Manufacturing","volume":"96 1","pages":"157-163"},"PeriodicalIF":0.0,"publicationDate":"2009-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81168331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 17

An Empirical Comparison of Spatial Randomness Models for Yield Analysis 产量分析的空间随机模型的实证比较

IEEE Transactions on Electronics Packaging Manufacturing Pub Date : 2009-04-03 DOI: 10.1109/TEPM.2009.2015768

H.H. Fellows, C. Mastrangelo, K. P. White

引用次数: 6

Effects of Anisotropic Conductive Film Viscosity on ACF Fillet Formation and Chip-On-Board Packages 各向异性导电膜粘度对ACF圆角形成和片上封装的影响

IEEE Transactions on Electronics Packaging Manufacturing Pub Date : 2009-03-31 DOI: 10.1109/TEPM.2009.2015288

Kyung-Woon Jang, K. Paik

引用次数: 17

Near Void-Free Assembly Development of Flip Chip Using No-Flow Underfill 采用无流底填的倒装芯片近无空隙组装开发

IEEE Transactions on Electronics Packaging Manufacturing Pub Date : 2009-03-27 DOI: 10.1109/TEPM.2009.2015592

Sangil Lee, M. Yim, R. Master, C. Wong, D. Baldwin

{"title":"Near Void-Free Assembly Development of Flip Chip Using No-Flow Underfill","authors":"Sangil Lee, M. Yim, R. Master, C. Wong, D. Baldwin","doi":"10.1109/TEPM.2009.2015592","DOIUrl":"https://doi.org/10.1109/TEPM.2009.2015592","url":null,"abstract":"The advanced flip-chip-in-package (FCIP) process technology, using no-flow underfill material for high I/O density (over 3000 I/O) and fine-pitch (down to 150 mum) interconnect applications, presents challenges for flip chip processing because underfill void formation during reflow drives interconnect yield down and degrades reliability. In spite of such challenges, a high yield, reliable assembly process (>99.99%) has been achieved using commercial no-flow underfill material with a high I/O, fine-pitch FCIP. This has been obtained using design of experiments with physical interpretation techniques. Statistical analysis determined what assembly conditions should be used in order to achieve robust interconnects without disrupting the FCIP interconnect structure. However, the resulting high yield process had the side effect of causing a large number of voids in the FCIP assemblies. Parametric studies were conducted to develop assembly process conditions that would minimize the number of voids in the FCIP induced by thermal effects. This work has resulted in a significant reduction in the number of underfill voids. This paper presents systematic studies into yield characterization, void formation characterization, and void reduction through the use of structured experimentation which was designed to improve assembly yield and to minimize the number of voids, respectively, in FCIP assemblies.","PeriodicalId":55010,"journal":{"name":"IEEE Transactions on Electronics Packaging Manufacturing","volume":"51 1","pages":"106-114"},"PeriodicalIF":0.0,"publicationDate":"2009-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78288163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Parameter Modeling for Wafer Probe Test 晶圆探头测试参数建模

IEEE Transactions on Electronics Packaging Manufacturing Pub Date : 2009-03-27 DOI: 10.1109/TEPM.2009.2017514

Y. Liu, T. Luk, S. Irving

{"title":"Parameter Modeling for Wafer Probe Test","authors":"Y. Liu, T. Luk, S. Irving","doi":"10.1109/TEPM.2009.2017514","DOIUrl":"https://doi.org/10.1109/TEPM.2009.2017514","url":null,"abstract":"This paper presents the simulation of parameters for wafer probe test by finite-element modeling with consideration of probe over-travel (OT) distance, scrub, contact friction coefficient, probe tip shapes, and diameter. The goal is to minimize the stresses in the device under the bond pad and eliminate wafer failure in probe test. In the probe test modeling, a nonlinear finite-element contact model is developed for the probe tip and wafer bond pad. Modeling results have shown that the probe test OT, probe tip shape and tip diameters, contact friction between the probe tip and bond pad, as well as the probe scrub of the probe tip on bond pad are important parameters that impact the failure of interlayer dielectric (ILD) layer under bond pad. Comparison between probe test damage and wire bonding failure shows the degree of damage to both probe test and wire bonding on the same bond pad structures. In addition that, a design of experiment (DOE) probe test with different ILD and metal thickness is carried. The correlation between the modeling and the DOE test is studied. The results show that the modeling solution agrees with the DOE probe test data. Modeling results have further revealed that probe test can induce the local tensile (or bending) first principal stress in ILD layer, which may be a root cause of the ILD failure in probe test.","PeriodicalId":55010,"journal":{"name":"IEEE Transactions on Electronics Packaging Manufacturing","volume":"266 ","pages":"81-88"},"PeriodicalIF":0.0,"publicationDate":"2009-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TEPM.2009.2017514","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72435105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Statistical Analysis of Transponder Packaging in UHF RFID Systems 超高频RFID系统中应答器封装的统计分析

IEEE Transactions on Electronics Packaging Manufacturing Pub Date : 2009-02-10 DOI: 10.1109/TEPM.2009.2012865

L. Mats, J. T. Cain, M. Mickle

引用次数: 3

Modeling of Soldering Quality by Using Artificial Neural Networks 基于人工神经网络的焊接质量建模

IEEE Transactions on Electronics Packaging Manufacturing Pub Date : 2009-02-10 DOI: 10.1109/TEPM.2008.2011813

M. Liukkonen, T. Hiltunen, Elina Havia, H. Leinonen, Y. Hiltunen

引用次数: 25

Geometric Analysis and Manufacturing Considerations for Optimizing the Characteristics of a Twisted Pair 优化双绞线特性的几何分析与制造考虑

IEEE Transactions on Electronics Packaging Manufacturing Pub Date : 2009-01-09 DOI: 10.1109/TEPM.2008.2005779

A. Lago, C. Peñalver, J. Marcos, J. Doval‐Gandoy, A. Melendez, Ó. López, F. Santiago, F. Freijedo, J. Vilas, J.C. Lorenzo

{"title":"Geometric Analysis and Manufacturing Considerations for Optimizing the Characteristics of a Twisted Pair","authors":"A. Lago, C. Peñalver, J. Marcos, J. Doval‐Gandoy, A. Melendez, Ó. López, F. Santiago, F. Freijedo, J. Vilas, J.C. Lorenzo","doi":"10.1109/TEPM.2008.2005779","DOIUrl":"https://doi.org/10.1109/TEPM.2008.2005779","url":null,"abstract":"The geometry of a twisted pair largely determines its electrical characteristics. To improve and refine the value of these characteristics according to preset values, the optimization of the manufacturing processes requires comprehensive knowledge of twisted pair geometry and of how electrical magnitudes are affected by the construction features of the twisted pair. This paper studies the relation between the length of a twisted pair cable and the length of each of the wires that compose the cable, by analyzing concepts such as pitch angle and radius of the helix. In addition, it examines the deformations and irregularities that can occur in the twisted pair during the manufacturing process and their effects on the geometry of the twisted pair. Results showed in this paper are a part of a larger research project carried out in association with the R&D department of a cable manufacturing company, and these results are being applied into the design department of this company.","PeriodicalId":55010,"journal":{"name":"IEEE Transactions on Electronics Packaging Manufacturing","volume":" 47","pages":"22-31"},"PeriodicalIF":0.0,"publicationDate":"2009-01-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TEPM.2008.2005779","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72379462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9