IEEE Transactions on Electronics Packaging Manufacturing最新文献

{"title":"Board-Level Vibration Failure Criteria for Printed Circuit Assemblies: An Experimental Approach","authors":"R. Amy, G. Aglietti, G. Richardson","doi":"10.1109/TEPM.2010.2084092","DOIUrl":"https://doi.org/10.1109/TEPM.2010.2084092","url":null,"abstract":"The assessment of the capability of electronic equipment, to withstand harsh vibration environments, is an issue faced in several branches of engineering. Various researchers have studied the vibration response of electronic boards using different parameters, e.g., local board accelerations, bending moments, curvatures, etc., as a simpler alternative to very detailed stress analysis. However, the issue of what parameter best correlates with vibration failures remains open. This paper investigates this specific problem using an experimental approach to assess whether it is possible to correlate failures produced by intense vibrations, with a single macroscopic parameter such as the local board acceleration, curvature, or surface strain. Printed circuit boards populated with a grid of electronic components (20 different types and 32 identical components per type) have been subjected to vibration testing and the results show that there is a very good correlation between the board curvature (and its surface strain) and failures of the electronics. The work also shows that-for the components tested here-local board acceleration cannot be used to predict components failures. Although this research has focused on a particular set of components, these are representative of typical classes of electronic components, and therefore it should be possible to generalize the conclusions to similar hardware.","PeriodicalId":55010,"journal":{"name":"IEEE Transactions on Electronics Packaging Manufacturing","volume":"26 1","pages":"303-311"},"PeriodicalIF":0.0,"publicationDate":"2010-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81720254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Editorial - CPMT Society to Merge Transactions in 2011","authors":"R. Johnson","doi":"10.1109/TEPM.2010.2087070","DOIUrl":"https://doi.org/10.1109/TEPM.2010.2087070","url":null,"abstract":"As of January 2011, the Transactions On Advanced Packaging, Transactions On Components And Packaging Technologies, and Transactions On Electronics Packaging Manufacturing will merge and be published as a single transactions. The new transactions will be titled: Transactions On Components, Packaging, And Manufacturing Technology.","PeriodicalId":55010,"journal":{"name":"IEEE Transactions on Electronics Packaging Manufacturing","volume":"40 1","pages":"241-242"},"PeriodicalIF":0.0,"publicationDate":"2010-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74021062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An Integrated Manufacturing System for the Design, Fabrication, and Measurement of Ultra-Precision Freeform Optics","authors":"L. Kong, C. Cheung, W. Lee, S. To","doi":"10.1109/TEPM.2010.2052811","DOIUrl":"https://doi.org/10.1109/TEPM.2010.2052811","url":null,"abstract":"Geometry complexity and high-precision requirement have imposed a lot of challenges for the design, manufacturing, and measurement of ultra-precision freeform surfaces with submicrometer form accuracy and surface finish in nanometer range. Successful manufacturing of ultra-precision freeform surface not only relies on the high precision of machine tools, but also largely depends on comprehensive consideration of advanced optics design, modeling, and optimization of the machining process, freeform surface measurement and characterization. Currently, there is still a lack of an integrated system to fill the gap between those different important stages for producing a complete optics part. This paper presents the theoretical basis for the establishment of an integrated platform for the design, fabrication, and measurement of ultra-precision freeform surfaces. The platform mainly consists of four key modules, which are optics design module, data exchange module, machining process simulation and optimization module and freeform measurement and evaluation module. A series of experiments have been conducted to evaluate the performance of the platform and its capability is realized through a trial implementation in the design, fabrication and measurement of an F-theta lens. The predicted values by the models in the system are found to agree well with the experimental results, and the freeform characterization results are also validated by the experiments. These show that the proposed integrated platform not only helps to shorten the cycle time for the development of freeform components but also provides an important means for optimizing the surface quality in the ultra-precision machining of freeform surfaces. With this system, optimal machining parameters, the best cutting strategy, and the optimization of the surface quality can be obtained without the need for conducting time-consuming and expensive cutting tests. This contributes to the advancement of the manufacturing and measurement technologies for the ultra-precision freeform surfaces.","PeriodicalId":55010,"journal":{"name":"IEEE Transactions on Electronics Packaging Manufacturing","volume":"92 1","pages":"244-254"},"PeriodicalIF":0.0,"publicationDate":"2010-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76568765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Signal Integrity Enhanced EBG Structure With a Ground Reinforced Trace","authors":"Sang-Gyu Kim, H. Kim, Hee-Do Kang, J. Yook","doi":"10.1109/TEPM.2010.2064778","DOIUrl":"https://doi.org/10.1109/TEPM.2010.2064778","url":null,"abstract":"In general, a conventional electromagnetic bandgap (EBG) structure efficiently suppresses simultaneous switching noise (SSN) over a wide frequency range. However, it is difficult to apply the geometry to the design of a real printed circuit boards (PCBs) for high-speed digital circuits due to the degradation in the signal integrity performance. In this paper, a ground reinforced trace (GRT) is added to the EBG power plane to guarantee power integrity (PI) as well as signal integrity (SI) simultaneously. In addition, the definition of a noise suppression bandwidth in an EBG structure is derived for the purpose of analyzing the correlation between the GRT and the noise suppression bandwidth. This correlation is utilized to decide the location of the GRT to mitigate the degradation of the low-pass cutoff frequency. As a result, an excellent signal performance is achieved without any degradation of the noise suppression bandwidth in a conventional EBG structure.","PeriodicalId":55010,"journal":{"name":"IEEE Transactions on Electronics Packaging Manufacturing","volume":"49 1","pages":"284-288"},"PeriodicalIF":0.0,"publicationDate":"2010-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76334682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Reducing Solder Paste Inspection in Surface-Mount Assembly Through Mahalanobis–Taguchi Analysis","authors":"J. C. Huang","doi":"10.1109/TEPM.2010.2055873","DOIUrl":"https://doi.org/10.1109/TEPM.2010.2055873","url":null,"abstract":"Increased functional density and reduced input/output (I/O) spacing are the market trends in the electronics manufacturing industry. Industry reports indicate that approximately 50%-70% of soldering defects are attributed to the solder paste printing process for printed circuit board (PCB) assembly. Hence, after the printing process, a solder paste inspection (SPI) system is generally used to examine the amount of solder paste deposition. Effective selection of components and bonding pads during solder inspection is extremely important in achieving desired process cycle times and ensuring assembly yield. This paper uses the Mahalanobis-Taguchi system to establish a systematic approach to determining guidelines for solder paste inspection. Among a total of 203 bonding pads on the board for a GPS product, the optimal model suggests that the solder deposition of 121 bonding pads be inspected. The reduction ratio is 40.4%, and the feasibility of the proposed model is verified. Also, for those bonding pads to be inspected for their solder paste deposition, this study uses empirical data to define the specifications to effectively distinguish acceptable PCB samples from defective. The threshold is within the 100% capability for judgment of solder paste printing quality in the surface mount assembly process.","PeriodicalId":55010,"journal":{"name":"IEEE Transactions on Electronics Packaging Manufacturing","volume":"66 1","pages":"265-274"},"PeriodicalIF":0.0,"publicationDate":"2010-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91396831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Scalability of Roll-to-Roll Gravure-Printed Electrodes on Plastic Foils","authors":"J. Noh, Dongsun Yeom, Chaemin Lim, Hwajin Cha, J. Han, Junseok Kim, Yongsu Park, V. Subramanian, Gyoujin Cho","doi":"10.1109/TEPM.2010.2057512","DOIUrl":"https://doi.org/10.1109/TEPM.2010.2057512","url":null,"abstract":"Roll-to-roll (R2R) gravure printing is considered to be a leading technology for the production of flexible and low-cost printed electronics in the near future. To enable the use of R2R gravure in printed electronics, the limits of overlay printing registration accuracy (OPRA) and the scalability of printed features with respect to the physical parameters of the gravure system, including given plastic substrates and inks, should be characterized. Important parameters of printed lines include surface roughness, thickness, line widening, and line-edge roughness. To date, there are no comprehensive reports regarding the limits of OPRA and the scalability of printed electrodes, including the control of surface roughness, thickness, line widening, and line-edge roughness using R2R gravure printing. In this paper, we examine ways of evaluating the OPRA limit of our gravure system. We find that OPRA is limited in the web moving direction to 40 μm and in the perpendicular direction to 16 μm, showing the importance of web handling on registration. Furthermore, we demonstrate the scalability of printed electrodes formed using a R2R gravure system to linewidths of 317 μm, with 440 nm thickness, 30 nm of surface roughness and edge waviness of 4 μm on PET foils, and describe optimization strategies to realize improved surface roughness, thickness, line widening, and line-edge roughness for future printed electronics applications.","PeriodicalId":55010,"journal":{"name":"IEEE Transactions on Electronics Packaging Manufacturing","volume":"59 1","pages":"275-283"},"PeriodicalIF":0.0,"publicationDate":"2010-08-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89157146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Simulation Methods for Predicting Fusing Current and Time for Encapsulated Wire Bonds","authors":"A. Mallik, R. Stout","doi":"10.1109/TEPM.2010.2055568","DOIUrl":"https://doi.org/10.1109/TEPM.2010.2055568","url":null,"abstract":"Wirebonding is a process often used to provide electrical connection between the silicon chip and the external leads of a semiconductor device using very fine wires. For high-power IC chips, as device size inevitably decreases, the wire diameter unfortunately must decrease due to the need of finer pitch wires. Fusing or melting of wirebonds thus increasingly becomes one of the potential failure issues for such ICs. This paper presents a finite element model that correlates very well with the observed maximum operating currents for such wirebonds under actual experimental test conditions. Aluminum, gold, and copper wires of different dimensions have been considered. The simulations have been done for transient as well as steady state, both for wires in air, and encapsulated in molding compounds.","PeriodicalId":55010,"journal":{"name":"IEEE Transactions on Electronics Packaging Manufacturing","volume":"106 1","pages":"255-264"},"PeriodicalIF":0.0,"publicationDate":"2010-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79289426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Electrical Shorting Propensity of Tin Whiskers","authors":"Sungwon Han, M. Osterman, M. Pecht","doi":"10.1109/TEPM.2010.2053377","DOIUrl":"https://doi.org/10.1109/TEPM.2010.2053377","url":null,"abstract":"When a tin whisker bridges two differently biased conductors, an electrical short is not guaranteed. In many instances, the voltage must exceed a threshold level in order to produce current flow due to weak physical contact and the presence of a non-conductive film such as an oxide layer. This paper presents a study that examines the breakdown voltage of tin whiskers and its relation to contact force. Whisker contact force studies were conducted using gold- and tin-coated tungsten probes, and the breakdown voltage was measured using a semiconductor parameter analyzer. It was verified that contact force is a critical factor in determining the type of current-voltage transition and level of breakdown voltage. Lower contact force between the probe and the whiskers caused the multiple transitions in current-voltage characteristics. The tin oxide layers on whiskers were analyzed using field emission transmission electron microscopy (FE-TEM).","PeriodicalId":55010,"journal":{"name":"IEEE Transactions on Electronics Packaging Manufacturing","volume":"12 1","pages":"205-211"},"PeriodicalIF":0.0,"publicationDate":"2010-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82588757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Formation and Growth of Intermetallic Compounds in Cu–Au and Au–Al Systems for Copper on Gold Bonding","authors":"Yingwei Jiang, Ronglu Sun, Youmin Yu, Zhijie Wang, Weimin Chen","doi":"10.1109/TEPM.2010.2053544","DOIUrl":"https://doi.org/10.1109/TEPM.2010.2053544","url":null,"abstract":"Copper (Cu) ball on gold (Au) bump (COG) bonding is developed as a practicable approach to solving the challenges posed by Cu wire bonding on large integrated circuit devices. In the COG bonding, there are two different interfaces, Cu-Au and Au-Al couples, which is totally different from either Cu or Au wire bonding. In this paper, the COG bonding was studied on a typical experimental chip of 69-μm bond pad opening and four-layer central via pattern design with current wire bonders. Tests of wire pull, ball shear, and crater were adopted in investigating the bonding strength at the interfaces and the potential damage of the underlying metals of bond pads after the COG bonding. The intermetallic compounds (IMCs) formation at the two interfaces, Cu-Au and Au-Al couples, were studied in detail on the cross-sectioned assembled samples. Two reliability tests, high-temperature baking (HTB) and temperature cycle (TC) were also used to investigate the IMC change and growth. The results showed that qualified bonding strength on all of bond pads existed and no damage such as crack and crater was observed on the underlying metals of the bond pads after removing Al metallization. At the Au-Al interface, a comparable Au-Al IMC was formed on as-bonded samples, and it gradually grew thick after the reliability tests and its corresponding content also changed along with temperature and time. At the Cu-Au interface, there was no observable formation of Cu-Al IMC on as-bonded samples. Undergoing 1008 hours HTB at 175°C, only a very thin Cu-Au IMC appeared at the Cu-Au interface. After all, the Cu-Au IMC appearance hardly affects the IC's mechanical performance.","PeriodicalId":55010,"journal":{"name":"IEEE Transactions on Electronics Packaging Manufacturing","volume":"24 1","pages":"228-235"},"PeriodicalIF":0.0,"publicationDate":"2010-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78655318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Introduction to the Special Issue on Tin Whiskers","authors":"M. Osterman","doi":"10.1109/TEPM.2010.2063670","DOIUrl":"https://doi.org/10.1109/TEPM.2010.2063670","url":null,"abstract":"The seven papers in this special section focus on research related to tin whisker growth and mitigation.","PeriodicalId":55010,"journal":{"name":"IEEE Transactions on Electronics Packaging Manufacturing","volume":"6 1","pages":"157-158"},"PeriodicalIF":0.0,"publicationDate":"2010-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85665042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}