IEEE Transactions on Electronics Packaging Manufacturing最新文献

{"title":"Application of Wide-Band Material Characterization Methods to Printable Electronics","authors":"Vesa Pynttäri, Riku M. Mäkinen, V. Palukuru, Kauko Östman, Hannu Sillanpää, T. Kanerva, T. Lepistö, J. Hagberg, H. Jantunen","doi":"10.1109/TEPM.2010.2051809","DOIUrl":"https://doi.org/10.1109/TEPM.2010.2051809","url":null,"abstract":"In this paper, characterization methods are presented with results from test structures printed with varying printing parameters and materials. It is shown that different process parameters affect both physical and electrical material properties and hence high-frequency material characterization is a vital part of the process providing important information for design purposes. The conductivities and loss information of nanoparticle inks and properties of dielectric material are achieved in addition to structural properties. In particular, dc measurement results from 1.1e7 S/m to 3.7e7 S/m and high-frequency attenuation values from 0.5 dB/cm to 2.8 dB/cm (at 10 GHz) are achieved for printed conductors.","PeriodicalId":55010,"journal":{"name":"IEEE Transactions on Electronics Packaging Manufacturing","volume":"148 1","pages":"221-227"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88661772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Environmental Influence on Sn Whisker Growth","authors":"A. Dimitrovska, R. Kovacevic","doi":"10.1109/TEPM.2010.2048034","DOIUrl":"https://doi.org/10.1109/TEPM.2010.2048034","url":null,"abstract":"This paper considers the influence of 1) humidity and 2) acidic humidity on the growth of Sn whiskers. Sn whisker morphology was observed over a six-month period. The results show that the electroplated surfaces exposed to pure humidity are populated with Sn whiskers dimensionally smaller than surfaces exposed to acidic humidity. Variables analyzed include surface condition, Cu-Sn inter-metallic formation at the film/substrate interface by X-ray Diffraction (XRD), and film thickness.","PeriodicalId":55010,"journal":{"name":"IEEE Transactions on Electronics Packaging Manufacturing","volume":"16 1","pages":"193-197"},"PeriodicalIF":0.0,"publicationDate":"2010-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82442144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Effects of Vacuum Ultraviolet Surface Treatment on the Bonding Interconnections for Flip Chip and 3-D Integration","authors":"K. Sakuma, J. Mizuno, N. Nagai, N. Unami, S. Shoji","doi":"10.1109/TEPM.2010.2048917","DOIUrl":"https://doi.org/10.1109/TEPM.2010.2048917","url":null,"abstract":"This paper focuses on the effects of a vacuum ultraviolet (VUV) surface treatment process on the interconnections for flip chip and 3-D integration. Organic contaminants that hinder reliable bonding are broken down and eliminated from the bumps and pad surfaces by irradiation with UV light at a wavelength of 172 nm at room temperature. There is no charge buildup, no temperature increase, and no ion bombardment damage during the process. Two different VUV cleaning conditions, with N2 or O2 gas in the vacuum chamber, were compared and evaluated. Samples of flip chip with Cu/Sn bumps and Au surface substrate were examined by measurement of contact angle, X-ray photoelectron spectroscopy (XPS), scanning electron microscopy (SEM), and atomic force microscopy (AFM) before and after VUV surface treatment. Cleaning times and ambient conditions have dramatic effects on the surface contact angles. The photoelectron spectra of C 1s were obtained by XPS analysis for information on the chemical species and the XPS results showed a reduction in surface carbon for both Au and Cu/Sn after the cleaning. The evidence indicates cleavage of the carbon-carbon bonds in the organic molecules occurs during the cleaning process. From the shear test results, it appears that VUV treatment improves the Cu/Sn-bump bonding strength, making it two times larger than for untreated samples. No delamination or obvious voids were detected on the bonding interface by Scanning acoustic microscopy (SAM) and cross-sectional SEM analysis. The experiments show that the VUV cleaning can effectively remove the organic contaminants on the surface of the bonding pads and improve the bonding strength.","PeriodicalId":55010,"journal":{"name":"IEEE Transactions on Electronics Packaging Manufacturing","volume":"31 1","pages":"212-220"},"PeriodicalIF":0.0,"publicationDate":"2010-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90568807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High Lateral Resolution Auger Electron Spectroscopic (AES) Measurements for Sn Whiskers on Brass","authors":"M. Bozack, E. R. Crandall, C. L. Rodekohr, R. Dean, G. Flowers, J. Suhling","doi":"10.1109/TEPM.2010.2048217","DOIUrl":"https://doi.org/10.1109/TEPM.2010.2048217","url":null,"abstract":"We report high lateral resolution Auger electron spectroscopic (AES) measurements on high aspect ratio Sn whiskers. The whiskers were grown from compressively stressed thin films (~ 6000 Å) of Sn on brass using a magnetron sputtering system. The Auger spectra show that, after sputter cleaning, the whisker is nearly 100% Sn at all locations along the whisker shaft, at the growing blunt end of the shaft, and with depth (~ 1000 Å) into the side of the whisker. The “as received” Sn whisker surface shows the expected ~ 200 Å of native Sn oxide at all locations and the O signal nearly disappeared (~ 3 atom%) after 200 Å of sputter cleaning. There was no evidence of high amounts of oxygen within the bulk of the whisker. That brass is not observed in the whisker shaft supports the notion that whisker formation is accompanied by material mass transport through interfaces and grain boundaries which causes stress (usually compressive) relief. This is supported by the most remarkable aspect of the whisker growth; namely, that high aspect ratio Sn whiskers ~ 100-500 μm in length containing no brass can be grown from a ~ 0.6 μm thin film of Sn.","PeriodicalId":55010,"journal":{"name":"IEEE Transactions on Electronics Packaging Manufacturing","volume":"39 1","pages":"198-204"},"PeriodicalIF":0.0,"publicationDate":"2010-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86123564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Defect Morphology and Texture in Sn, Sn–Cu, and Sn–Cu–Pb Electroplated Films","authors":"P. Sarobol, A. Pedigo, P. Su, J. Blendell, C. Handwerker","doi":"10.1109/TEPM.2010.2046172","DOIUrl":"https://doi.org/10.1109/TEPM.2010.2046172","url":null,"abstract":"In this paper, the concept of a defect phase diagram is introduced which quantifies the effects of Cu and Pb additions to electrodeposited Sn films on surface defect formation, including but not limited to the formation of Sn whiskers. Transitions were observed in both the defect densities and the morphologies of hillocks and whiskers as Cu and Pb film compositions were systematically varied. Changes in crystallographic texture were also reported for a subset of the Sn-Cu-Pb alloys examined. The transitions between different defect types and the coexistence of certain defect types help to interpret the role of grain boundary pinning in hillock and whisker formation.","PeriodicalId":55010,"journal":{"name":"IEEE Transactions on Electronics Packaging Manufacturing","volume":"6 1","pages":"159-164"},"PeriodicalIF":0.0,"publicationDate":"2010-04-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74464413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Study of 6 mil Cu Wire Replacing 10–15 mil Al Wire for Maximizing Wire-Bonding Process on Power ICs","authors":"Yingwei Jiang, Ronglu Sun, Youmin Yu, Zhijie Wang","doi":"10.1109/TEPM.2010.2045760","DOIUrl":"https://doi.org/10.1109/TEPM.2010.2045760","url":null,"abstract":"Copper (Cu) wire-bonding with its advantage in cost, mechanical enhanced characteristic, and better electrical performance is a developing alternative interconnection technology to replace gold (Au) and aluminum (Al) wires in IC packaging manufacturing. This paper discussed the experimental study of using 6-mil Cu wire on an ASM wire bonder to replace 10-15 mil Al wire in a power IC device. It encompassed wire and tool selection, wire-bonding process development, post wire-bonding integrity inspection, and bonding reliability results. The wire and tool selection included type of wire, capillary use, and bonder capability. The process development focused on two crucial stages, Free air ball (FAB) formation and bonding process window development. Design of experiment (DOE) was extensively applied in this study. The experimental studies showed that flow rate of forming gas was a key factor to form the qualified FABs and establishment of a workable process window. Wire pull and ball shear tests were conducted per JEDEC criteria for bond strength integrity. Moreover, crater test and Zygo's 3-D measurement were used to inspect any risk of underlying metal integrity in die before reliability tests. The data showed that sufficient thickness of the Al bond pad was crucial to avoid any underlying metal damage when subjected to heavy copper wire bonding forces. High-temperature baking (HTB) and pre-condition (PC) and temperature cycle (TC) were used to evaluate the samples reliability. The results of the two reliability tests showed that Cu/AL intermetallic compound (IMC) growth was slow, which indicates potential significant product life-span extension. The study concluded that with current thermosonic ball bonder, using 6-mil Cu wire could replace heavy 10-15 mil Al wire in power IC applications.","PeriodicalId":55010,"journal":{"name":"IEEE Transactions on Electronics Packaging Manufacturing","volume":"1 1","pages":"135-142"},"PeriodicalIF":0.0,"publicationDate":"2010-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89459886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Evolutionary Path Planning With Subpath Constraints","authors":"J. S. Gyorfi, D. Gamota, S. Mok, J. Szczech, M. Toloo, J. Zhang","doi":"10.1109/TEPM.2010.2046327","DOIUrl":"https://doi.org/10.1109/TEPM.2010.2046327","url":null,"abstract":"We develop an evolutionary method of planning paths that are subject to subpath constraints. These constraints can include subpaths that must be incorporated into the solution path, path intersection restrictions, and obstacle avoidance. Our method involves two stages. In the first stage, a global solution is found without consideration of any obstacles. In the second stage, local planning is performed to modify the global path to avoid obstacles. Stage one involves a fixed-length chromosome formulation of a genetic algorithm that utilizes existing operators and a new subpath reversal operator. Stage two involves a graph search process. Our algorithm is applicable to the field of printed electronics where continuous-spray processes are used to deposit electrically functional material onto flexible substrates. These processes give rise to the kinds of subpath constraints we have investigated. We evaluate our algorithm by applying it to a representative problem in the printed electronics field.","PeriodicalId":55010,"journal":{"name":"IEEE Transactions on Electronics Packaging Manufacturing","volume":"35 1","pages":"143-151"},"PeriodicalIF":0.0,"publicationDate":"2010-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84420274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Correlation Between Whisker Initiation and Compressive Stress in Electrodeposited Tin–Copper Coating on Copper Leadframes","authors":"Takahiko Kato, H. Akahoshi, Masato Nakamura, T. Terasaki, T. Iwasaki, T. Hashimoto, A. Nishimura","doi":"10.1109/TEPM.2010.2045384","DOIUrl":"https://doi.org/10.1109/TEPM.2010.2045384","url":null,"abstract":"To evaluate the contribution of coating stress to whisker initiation from IC package leads, the stress distribution in the coating was investigated by finite-element analysis (FEA). Two different leadframe samples, which were composed of the same tin-copper coating on two different copper-leadframe materials, namely, copper-iron (hereafter, CUFE; corresponding to CDA number C19400) and copper-chromium (CUCR; CDA number C18045), were used to examine the whisker-initiation behavior on the coating surfaces. The two samples showed significantly different tendencies of whisker initiation from the coating. That is, after long-term storage at room temperature, no whisker initiation was observed on the coating on the CUCR sample, whereas long whiskers (with a maximum length of more than 200 μm) were formed from the coating on the CUFE sample. The FEA calculation on the leadframe samples revealed that the coatings had a two-directional stress gradient, namely, one gradient toward the surface and another toward the base leadframe material. It also indicated a difference between the stress distributions in the two samples. The gradient of normal stress on the coating's grain boundaries (GBs), toward the surface of the CUFE sample, was found to be larger than that in the CUCR sample. This result implies that the tin-atom flux along a GB in the coating on the CUFE sample was larger than that on the CUCR sample because the atom flux along the GB was proportional to the stress gradient. It agrees with the above-mentioned whisker-initiation behaviors in the samples. We thus conclude that in the CUFE sample, a whisker initiates either from a surface grain immediately on top of a GB or from surface grains located on both sides of the same GB. To confirm this conclusion, the correlation between the tin-diffusion sites and whisker formation sites was investigated. Simulation of atom diffusion by molecular dynamics indicated that the dominant tin-diffusion site is a GB when compressive stress is applied in the direction normal to the GB. Investigation of the correlation between the whisker roots and coating microstructures of the CUFE sample showed that the whisker roots were located on top of GB intersections in the coating. These results indicate that whisker-initiation sites are correlated with dominant tin-diffusion sites and that each whisker initiates either from a surface grain located immediately on top of a GB or from surface grains located on both sides of the same GB.","PeriodicalId":55010,"journal":{"name":"IEEE Transactions on Electronics Packaging Manufacturing","volume":"69 1","pages":"165-176"},"PeriodicalIF":0.0,"publicationDate":"2010-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80351037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Application of the Underfill Model to Bump Arrangement and Dispensing Process Design","authors":"Sin-Wei Peng, W. Young","doi":"10.1109/TEPM.2010.2044648","DOIUrl":"https://doi.org/10.1109/TEPM.2010.2044648","url":null,"abstract":"Along with the technology advance, the applications of flip chip have the tendency toward lower profile, lighter weight, and higher density. Due to the mismatch of the coefficients of thermal expansion (CTE) between the chip and substrate, the solder joints tend to fail under high thermal stresses. In order to enhance the reliability of the solder joints, underfill encapsulation is filled into the gap between the chip and substrate around the solder joints by capillary force. It is crucial for flip-chip technology to speed up the encapsulation process and avoid the formation of voids at the same time. A finite-element model was developed to simulate the underfill flow in our laboratory. In this paper, further verification of the underfill model is performed to confirm its feasibility. A model is proposed to design an efficient process for encapsulant dispensing based on the underfill model. Application of the model is also conducted to investigate the effect of different bump designs on the dispensing process.","PeriodicalId":55010,"journal":{"name":"IEEE Transactions on Electronics Packaging Manufacturing","volume":"44 1","pages":"122-128"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84297159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Advanced Package Prototyping Using Nano-Particle Silver Printed Interconnects","authors":"Sungchul Joo, D. Baldwin","doi":"10.1109/TEPM.2010.2044887","DOIUrl":"https://doi.org/10.1109/TEPM.2010.2044887","url":null,"abstract":"To reduce manufacturing cost, lead time, and process complexity, an embedded-active approach that targets rapid prototyping and low-volume production in micro-system packaging is being developed. The approach involves a rapid prototyping of micro-system packaging by a data-driven chip-first packaging process using direct printing of nano-particle metals. In the chip-first process, bare dice are first embedded into a copper or stainless steel carrier substrate, fixed by filling the gap between the chips and the substrate with thermoplastic adhesives, and planarized to a common planar surface. On the coplanar substrate, polyimide film is laminated to form a dielectric layer. Through the dielectric layer to the chip metal pads, micro vias are drilled by laser ablation. The vias are filled with nano-particle silver (NPS). The NPS is deposited by screen printing or aerosol-jet printing and an electrical circuit is formed. This packaging approach is a dry process and it does not require any photo masks for circuit patterning, resulting in reducing packaging turn-around time from months to days. It is also less limited by substrate composition and morphology, eliminates the need for special chip processing such as flip chip solder bumps, and permits using any chip technology and any chip supplier allowing mixed devices. The embedded-active process with NPS avoids the extreme processing conditions required for standard IC fabrication such as wet chemistry processing and vacuum sputtering. The NPS can be sintered at plastic-compatible temperatures as low as 230?C to form material nearly indistinguishable from the bulk metal. The embedded-active packaging shows good reliability performance in terms of thermal shock, which is performed in the range of -40?C and 125?C. These results represent an important step to a system packaging characterized by high-density, low-cost, and data-driven fabrication for rapid package prototyping. This paper presents details of the rapid prototyping process sequence, an initial reliability characterization of the package architecture, and a failure mode analysis of the packages.","PeriodicalId":55010,"journal":{"name":"IEEE Transactions on Electronics Packaging Manufacturing","volume":"43 1","pages":"129-134"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84539318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}