Aeu-International Journal of Electronics and Communications最新文献_第6页

Beam upwarping suppression for the horizontal omnidirectional monopole antenna in broad bandwidth by using a composite structure

IF 3 3区计算机科学

Aeu-International Journal of Electronics and Communications Pub Date : 2025-02-08 DOI: 10.1016/j.aeue.2025.155715

Jiemin Jing, Wenquan Cao, Hong Xue, Chuang Wang, Yangkun Zhu, Huangshu Zhou, Yixin Tong

{"title":"Beam upwarping suppression for the horizontal omnidirectional monopole antenna in broad bandwidth by using a composite structure","authors":"Jiemin Jing, Wenquan Cao, Hong Xue, Chuang Wang, Yangkun Zhu, Huangshu Zhou, Yixin Tong","doi":"10.1016/j.aeue.2025.155715","DOIUrl":"10.1016/j.aeue.2025.155715","url":null,"abstract":"<div><div>Due to the ground plane effect, the horizontal omnidirectional pattern of the monopole antenna will tilt upwards, thereby affecting the communication quality in the horizontal direction. In this paper, one composite structure (CS) composed of mushroom structures (MSs) and parasitic metal pillar elements (PMPEs) is introduced, loading uniformly around the source antenna (SA) to suppress the beam upwarping. The individual MSs can enhance the current on the ground plane, coupling more electromagnetic energy to the horizontal plane in the band outside the bandgap. Meanwhile, the PMPEs act as directors, guiding the space wave energy along the horizontal plane in a wide band. By using the two structures as one CS together, beam upwarping suppression is realized for the monopole antenna in broad bandwidth. This structure can achieve 4–25° of suppression at 410–522 MHz and 0.97–2.3 dB improvement on the horizontal plane gain, which is much better than the condition when the two structures are loaded alone. The experimental results prove the theoretical analysis. This structure can provide more stable communication for the design of high-performance devices.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"192 ","pages":"Article 155715"},"PeriodicalIF":3.0,"publicationDate":"2025-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143403155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 10 mW-output power range and 88.1% efficiency reconfigurable DC-DC converter with clockless-sampling and pile-up technique for dual-source energy harvesting

IF 3 3区计算机科学

Aeu-International Journal of Electronics and Communications Pub Date : 2025-02-07 DOI: 10.1016/j.aeue.2025.155700

Tong Liu, Zilin Yang, Jiale Zhu, Xiaofei Chen, Yanhan Zeng

引用次数: 0

Low-cost linearity range LVDT read-out circuit using LC Wien bridge oscillator and microcontroller with parasitic insensitive

IF 3 3区计算机科学

Aeu-International Journal of Electronics and Communications Pub Date : 2025-02-05 DOI: 10.1016/j.aeue.2025.155699

Preecha Thongdit , Krit Angkeaw

引用次数: 0

Programmable CMOS current signal generator for simultaneous multi-sine bioimpedance analysis

IF 3 3区计算机科学

Aeu-International Journal of Electronics and Communications Pub Date : 2025-02-05 DOI: 10.1016/j.aeue.2025.155701

Israel Corbacho, Juan M. Carrillo, José L. Ausín, Miguel Á. Domínguez, Raquel Pérez-Aloe, J. Francisco Duque-Carrillo

{"title":"Programmable CMOS current signal generator for simultaneous multi-sine bioimpedance analysis","authors":"Israel Corbacho, Juan M. Carrillo, José L. Ausín, Miguel Á. Domínguez, Raquel Pérez-Aloe, J. Francisco Duque-Carrillo","doi":"10.1016/j.aeue.2025.155701","DOIUrl":"10.1016/j.aeue.2025.155701","url":null,"abstract":"<div><div>A fully-differential CMOS current signal generator, suitable for on-chip simultaneous multi-sine bioimpedance spectroscopy, is presented. The proposal is based on generating sinusoidal voltage signals, which are converted into currents and summed in a multiple-input current driver. The oscillators rely on a transconductor-capacitor (<span><math><msub><mrow><mi>G</mi></mrow><mrow><mi>m</mi></mrow></msub></math></span>-<em>C</em>) structure, which allows low-power and wide-frequency-range features. Each input channel of the current driver is a linearized voltage-to-current converter, to deliver a highly-linear multi-sine excitation current. A common-mode feedback (CMFB) network is used to set the DC component of the output voltage, also leading to a high output impedance. The output current can be digitally programmed by means of a 3-bit control signal, which allows measuring a wide range of impedances under test. The circuit has been designed and fabricated in 180 nm CMOS technology to operate with a 1.8-V supply. The output resistance of the current driver has been found to be above 1 M<span><math><mi>Ω</mi></math></span> at low frequencies for the maximum output current of <span><math><mrow><mn>62</mn><mo>.</mo><mn>5</mn><mspace></mspace><mi>μ</mi><mi>A</mi></mrow></math></span> and it is kept higher than approximately 20 k<span><math><mi>Ω</mi></math></span> for a frequency equal to 1 MHz and the same output current level. The output current can be tuned in the range [9.7,62.5] <span><math><mi>μ</mi></math></span>A ensuring that the individual frequency components present a THD lower than <span><math><mo>−</mo></math></span>40 dB.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"192 ","pages":"Article 155701"},"PeriodicalIF":3.0,"publicationDate":"2025-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143372555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Electronically tunable Schmitt trigger with independent TL/TH and output level control using commercially available ICs

IF 3 3区计算机科学

Aeu-International Journal of Electronics and Communications Pub Date : 2025-02-04 DOI: 10.1016/j.aeue.2025.155710

Phamorn Silapan, Arisara Luewisutichat, Pawich Choykhuntod, Rapeepan Kaewon

引用次数: 0

Design, analysis and implementation of an optimized cost-effective octagonal patch antenna with UWB characteristics for 5G applications and beyond

IF 3 3区计算机科学

Aeu-International Journal of Electronics and Communications Pub Date : 2025-02-01 DOI: 10.1016/j.aeue.2024.155655

Hind Abbaoui , Salah Eddine EL Aoud , Syed Umaid Ali , Abdelilah Ghammaz , Hassan Belahrach , Saida Ibnyaich

{"title":"Design, analysis and implementation of an optimized cost-effective octagonal patch antenna with UWB characteristics for 5G applications and beyond","authors":"Hind Abbaoui , Salah Eddine EL Aoud , Syed Umaid Ali , Abdelilah Ghammaz , Hassan Belahrach , Saida Ibnyaich","doi":"10.1016/j.aeue.2024.155655","DOIUrl":"10.1016/j.aeue.2024.155655","url":null,"abstract":"<div><div>Microstrip patch antennas have recently garnered significant traction in the wireless communication field due to their cost-effectiveness, low profile, and ease of fabrication on circuit boards. In this context, an ultra-wideband (UWB), optimized, compact, octagonal-shaped microstrip patch antenna (OMPA) designed for multiple 5G, WiFi, and potential 6G uses are presented. The proposed antenna features dimensions of 21 × 23.52 × 1.6 mm<sup>3</sup>, corresponding to electrical measurements of 0.24λ × 0.27λ × 0.026λ. λ represents the free-space wavelength at the resonant frequency of 3.5 GHz. Also, the antenna is printed on a commercially available epoxy substrate with a 4.3 relative permittivity with the ground and radiating patch made of copper of 0.035 mm thickness. In addition, a partial ground structure is used to obtain omnidirectional radiation and miniaturization, while the rectangular slot in the ground greatly enhances the proposed antenna’s bandwidth. After the fabrication and testing of prototypes, the proposed antenna works throughout a frequency range. starting at 3.14 GHz to 13.5 GHz, reaching the entirety of 10 GHz of band with two resonant frequencies of 3.8 GHz and 8 GHz. With its high average efficiency, excellent reflection coefficient profiles and the optimal Voltage Standing Wave Ratio (VSWR) values, the optimized OMPA is a suitable antenna for high data-rate applications in 5G wireless communications operating at sub-6 GHz and sub-7 GHz. This research also highlights the antenna’s potential integration into future 6G standards.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"190 ","pages":"Article 155655"},"PeriodicalIF":3.0,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143183293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design and parametric characterization of CNTFET based stable static random access memory bit-cell for low-power applications

IF 3 3区计算机科学

Aeu-International Journal of Electronics and Communications Pub Date : 2025-02-01 DOI: 10.1016/j.aeue.2024.155642

Divyansh Yadav , Anuja Bhargava , Elangovan Mani , Ashish Sachdeva

{"title":"Design and parametric characterization of CNTFET based stable static random access memory bit-cell for low-power applications","authors":"Divyansh Yadav , Anuja Bhargava , Elangovan Mani , Ashish Sachdeva","doi":"10.1016/j.aeue.2024.155642","DOIUrl":"10.1016/j.aeue.2024.155642","url":null,"abstract":"<div><div>The Carbon Nanotube Field Effect Transistor (CNTFET) is rapidly emerging as an attractive alternative to traditional CMOS transistors. In this work, a stable Feedback Cutting, PPN inverter based 10 transistor (FCPPN10T) Static Random Access Memory (SRAM) bit-cell design based on CNTFETs has been designed for low-power operations. The proposed cell has been tested for key parametric variation of CNTFET transistors such as chiral vector, pitch, number of carbon nonotubes, dielectric constant, and oxide thickness. The proposed FCPPN10T SRAM cell improves read/write static noise margin by 1.98<span><math><mo>×</mo></math></span>/ 1.132<span><math><mo>×</mo></math></span>, respectively, at 0.3 V compared to conventional 6T SRAM that uses similar CNTFET parameters. The read/write delay of proposed FCPPN10T is higher by 1.03<span><math><mo>×</mo></math></span>/ 1.24<span><math><mo>×</mo></math></span>, respectively, at 0.3 V compared to conventional 6T SRAM. The leakage power of proposed design is improved by 4.118<span><math><mo>×</mo></math></span> compared to conventional 6T. The proposed design parameters are also compared with three pre-proposed SRAM bit-cells. The simulation is performed with the Cadence Virtuoso using the Stanford University 32 nm CNTFET Verilog model.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"190 ","pages":"Article 155642"},"PeriodicalIF":3.0,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143183575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A single-phase five-level multilevel inverter with rated power fault-tolerant feature

IF 3 3区计算机科学

Aeu-International Journal of Electronics and Communications Pub Date : 2025-02-01 DOI: 10.1016/j.aeue.2024.155645

Vemana Ramanarayana , Kudithi Nageswara Rao , Balram Kumar , S.V.K. Naresh

{"title":"A single-phase five-level multilevel inverter with rated power fault-tolerant feature","authors":"Vemana Ramanarayana , Kudithi Nageswara Rao , Balram Kumar , S.V.K. Naresh","doi":"10.1016/j.aeue.2024.155645","DOIUrl":"10.1016/j.aeue.2024.155645","url":null,"abstract":"<div><div>Multilevel inverters with fault-tolerance capabilities are critical for powering modern emergency loads, where reliability is the crucial parameter. For enhanced reliability, this paper introduces a single-phase five-level fault-tolerant multilevel inverter to ensure continuous operation even after the occurrence of the faults, while maintaining rated power output. The proposed converter achieves this feature by adopting redundant switches and triacs, which improves the fault-tolerant capability. This paper presents the detailed operating principle of the proposed converter, and its effectiveness is validated through the MATLAB/SIMULINK platform. Further, a 500 W prototype is developed and tested under normal and fault conditions. The experimental results confirmed that the proposed converter can be reconfigured to operate at rated power during faulty conditions. Furthermore, an extensive analysis of reliability, efficiency, and other performance metrics is presented to evaluate the superiority of the proposed converter. The advantages of the proposed converter make it an excellent choice for critical applications.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"190 ","pages":"Article 155645"},"PeriodicalIF":3.0,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143183578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Stoch-IMC: A bit-parallel stochastic in-memory computing architecture based on STT-MRAM

IF 3 3区计算机科学

Aeu-International Journal of Electronics and Communications Pub Date : 2025-02-01 DOI: 10.1016/j.aeue.2024.155614

Amir M. Hajisadeghi, Hamid R. Zarandi, Mahmoud Momtazpour

{"title":"Stoch-IMC: A bit-parallel stochastic in-memory computing architecture based on STT-MRAM","authors":"Amir M. Hajisadeghi, Hamid R. Zarandi, Mahmoud Momtazpour","doi":"10.1016/j.aeue.2024.155614","DOIUrl":"10.1016/j.aeue.2024.155614","url":null,"abstract":"<div><div>In-memory computing (IMC) offloads parts of the computations to memory to fulfill the performance and energy demands of applications such as neuromorphic computing, machine learning, and image processing. Fortunately, the main features that stochastic computing (SC) and IMC share, which are low computation complexity and high bit-parallel computation capability, promise great potential for integrating SC and IMC. In this paper, we exploit this potential by using stochastic computation as an approximation method to present effective in-memory computations with a good trade-off among design parameters. To this end, first, commonly used stochastic arithmetic operations of applications are effectively implemented using the primitive logic gates of the IMC method. Next, the in-memory scheduling and mapping of applications are obtained efficiently by a proposed algorithm. This algorithm reduces the computation latency by enabling intra-subarray parallelism while considering the IMC method constraints. Subsequently, a bit-parallel stochastic IMC architecture, Stoch-IMC, is presented that enables bit parallelization of stochastic computations over memory subarrays/banks. To evaluate Stoch-IMC’s effectiveness, various analyses were conducted. Results show average performance improvements of 135.7X and 124.2X across applications compared to binary IMC and related in-memory SC methods, respectively. The results also demonstrate an average energy reduction of 1.5X compared to binary IMC, with limited energy overhead relative to the in-memory SC method. Furthermore, the results reveal average lifetime improvements of 4.9X and 216.3X over binary IMC and in-memory SC methods, respectively, along with high bitflip tolerance.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"190 ","pages":"Article 155614"},"PeriodicalIF":3.0,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143183273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Second-generation voltage conveyor-based first-order all-pass filters and application to quadrature sinusoidal oscillator

IF 3 3区计算机科学

Aeu-International Journal of Electronics and Communications Pub Date : 2025-02-01 DOI: 10.1016/j.aeue.2024.155619

Winai Jaikla , Burin Theppota , Wiset Saksiri , Fabian Khateb , Montree Siripruchyanun

{"title":"Second-generation voltage conveyor-based first-order all-pass filters and application to quadrature sinusoidal oscillator","authors":"Winai Jaikla , Burin Theppota , Wiset Saksiri , Fabian Khateb , Montree Siripruchyanun","doi":"10.1016/j.aeue.2024.155619","DOIUrl":"10.1016/j.aeue.2024.155619","url":null,"abstract":"<div><div>This article describes 2 first-order voltage-mode all-pass filters (APFs) covering leading and lagging phases based on single capacitor and second-generation voltage conveyors (VCIIs). The proposed APFs comprise 2 VCIIs cooperating with 3 resistors and 1 capacitor. The phase angle of the output relative to input signals can be tuned by the single external resistor. Different from previously related works, they use only VCII+ which can be easily realized and less complicated for both integrated circuit architecture and off-the-shelf design. In addition, a 450 mV 1.98 µW VCII based on bulk-driven quasi-floating-gate MOS transistor was developed to be used in this work to achieve ultra low-voltage and low-power consumption. The proposed APFs offer a phase shifting function over a wide range of operating frequency. Its output also provides an accurate sinusoidal signal. The testing results obtained from Cadence Virtuoso System Design Platform simulation are disclosed to investigate different behaviors of the proposed APFs. In addition, the experimental setup using commercially available integrated circuits is shown. From the both results, it is found that they are agreed well with the mentioned anticipations. An application of the proposed APFs in quadrature sinusoidal oscillator is also depicted, it enjoys independent controllability of oscillation condition and oscillation frequency for a wide range of operating frequency with a precise quadrature output signal.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"190 ","pages":"Article 155619"},"PeriodicalIF":3.0,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143183451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0