Aeu-International Journal of Electronics and Communications最新文献_第5页

Miniaturized wideband bandpass filter using capacitor-loaded coupled-lines 使用电容耦合线的小型化宽带带通滤波器

IF 3 3区计算机科学

Aeu-International Journal of Electronics and Communications Pub Date : 2024-08-13 DOI: 10.1016/j.aeue.2024.155476

引用次数: 0

A vertical transition for suspended line with two transition modes 具有两种过渡模式的悬线垂直过渡装置

IF 3 3区计算机科学

Aeu-International Journal of Electronics and Communications Pub Date : 2024-08-13 DOI: 10.1016/j.aeue.2024.155478

引用次数: 0

On the integral and derivative identities of bivariate Fox H-function and applications in performance analysis of wireless communications under generalized Gaussian noise 论二元福克斯 H 函数的积分和导数等式及其在广义高斯噪声下无线通信性能分析中的应用

IF 3 3区计算机科学

Aeu-International Journal of Electronics and Communications Pub Date : 2024-08-12 DOI: 10.1016/j.aeue.2024.155481

引用次数: 0

A high-speed dynamic comparator with automatic offset calibration 带自动偏移校准功能的高速动态比较器

IF 3 3区计算机科学

Aeu-International Journal of Electronics and Communications Pub Date : 2024-08-10 DOI: 10.1016/j.aeue.2024.155472

引用次数: 0

A Σ-Δ ADC with a DPOQ system and a new multi-Stage digital filter 带有 DPOQ 系统和新型多级数字滤波器的 Σ-Δ ADC

IF 3 3区计算机科学

Aeu-International Journal of Electronics and Communications Pub Date : 2024-08-10 DOI: 10.1016/j.aeue.2024.155474

引用次数: 0

Guest editorial special issue on selected papers from SMACD 2023 SMACD 2023 论文选编特刊客座编辑

IF 3 3区计算机科学

Aeu-International Journal of Electronics and Communications Pub Date : 2024-08-08 DOI: 10.1016/j.aeue.2024.155471

引用次数: 0

Substrate integrated waveguide-based ultra-compact self-heptaplexing antenna for IoT connectivity 用于物联网连接的基底集成波导式超小型自七工天线

IF 3 3区计算机科学

Aeu-International Journal of Electronics and Communications Pub Date : 2024-08-06 DOI: 10.1016/j.aeue.2024.155465

{"title":"Substrate integrated waveguide-based ultra-compact self-heptaplexing antenna for IoT connectivity","authors":"","doi":"10.1016/j.aeue.2024.155465","DOIUrl":"10.1016/j.aeue.2024.155465","url":null,"abstract":"<div><p>This paper introduces an innovative design of a substrate-integrated waveguide (SIW)-based self-heptaplexing antenna (SHA). The proposed structure is implemented using a combination of circular and rectangular HM-SIW cavities. Furthermore, the antenna contains seven individual patches on top of the SIW cavity to operate at seven distinct frequencies. The microstrip feeding technique has been used to activate seven distinct ports. All patches are excited through 50-ohm feedlines. The antenna operation is elucidated using an equivalent LC model. To demonstrate its operating principles a self-heptaplexing antenna has been designed to work at 2.45, 3, 3.58, 4, 4.45, 5.2, and 5.88 GHz. The measured realized gain of the proposed antenna at the respective bands is 3.2, 3.85, 3.1, 3.245, 4, 2.98, and 4.5 dBi. The isolation exceeds 20 dB over the entire working bands. The EM-simulated and measured characteristics are in good agreement. Although the suggested antenna has been designed for seven ports and lower frequencies, it has a relatively compact size of 0.28 <span><math><msubsup><mrow><mi>λ</mi></mrow><mrow><mi>g</mi></mrow><mrow><mn>2</mn></mrow></msubsup></math></span>. The major advantages of the proposed self-heptaplexing antenna include excellent isolation, an ultra-compact design, and good radiation characteristics. The proposed antenna offers a high degree of flexibility. It allows for independent frequency tuning, which makes it suitable for IoT, wireless communication systems, and diverse sub-6 GHz band applications.</p></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":null,"pages":null},"PeriodicalIF":3.0,"publicationDate":"2024-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141934694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A class AB ultra-low-power asymmetrical structured current multiplier AB 类超低功耗非对称结构电流倍增器

IF 3 3区计算机科学

Aeu-International Journal of Electronics and Communications Pub Date : 2024-08-06 DOI: 10.1016/j.aeue.2024.155470

{"title":"A class AB ultra-low-power asymmetrical structured current multiplier","authors":"","doi":"10.1016/j.aeue.2024.155470","DOIUrl":"10.1016/j.aeue.2024.155470","url":null,"abstract":"<div><p>An ultra-low power (ULP) class-AB four-quadrant current multiplier is introduced with a new power and area-saving technique based on asymmetrical structures such as direct current copying (DCC) and an asymmetrical transconductor (A-g<sub>m</sub>). The DCC technique decreases the bias current and chip area by copying them directly from the lower current branches. Additionally; it enables direct voltage biasing and current branch elimination, resulting in lower decreased standby and dynamic power and smaller chip area. The newly released A-g<sub>m</sub>, featuring asymmetrical input transistors, enables a further reduction in current bias with minimal distortion but a higher input modulation index (M.I.) than previous works. Furthermore, a Wilson active load with modified transistor dimensions was applied to implement the structure in a conventional n-well 180 nm TSMC process. Simulation results verified by Cadence Virtuoso software demonstrate superior achievements in power and area compared to previous works, despite using a more backward technology. For a <span><math><mo>±</mo></math></span> 0.35 V voltage power supply, the multiplier has a 1.8 nW standby power and a total harmonic distortion (THD) of −30 dB for an input M.I. of 12.64.</p></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":null,"pages":null},"PeriodicalIF":3.0,"publicationDate":"2024-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142011417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A novel FVF-based GHz-range biquad in a 28 nm CMOS FD-SOI technology 28 纳米 CMOS FD-SOI 技术中基于 FVF 的新型 GHz 范围双四极管

IF 3 3区计算机科学

Aeu-International Journal of Electronics and Communications Pub Date : 2024-08-03 DOI: 10.1016/j.aeue.2024.155466

引用次数: 0

An ultra-low power adjustable current-mode analog integrated general purpose artificial neural network classifier 超低功耗可调电流模式模拟集成通用人工神经网络分类器

IF 3 3区计算机科学

Aeu-International Journal of Electronics and Communications Pub Date : 2024-08-03 DOI: 10.1016/j.aeue.2024.155467

{"title":"An ultra-low power adjustable current-mode analog integrated general purpose artificial neural network classifier","authors":"","doi":"10.1016/j.aeue.2024.155467","DOIUrl":"10.1016/j.aeue.2024.155467","url":null,"abstract":"<div><p>This study introduces a methodology tailored to analog hardware architecture for implementing an artificial neural network. The fundamental components of the architecture include current-mode circuits, representing the class, and a voltage-mode comparator. Specifically, the current mode circuits comprise the Mahalanobis distance circuit, Sigmoid function circuit, analog multiplier, and current mirrors. Regarding the voltage comparator, which receives the final decision, a folded-cascode operational amplifier is employed. The operational principles of the architecture are extensively explained and applied in a power-efficient configuration (operating under 976nW) with low power supply rails (0.6 V). The proposed implementation is tested on real-world biomedical classification tasks, achieving classification accuracy exceeding 91.6%. The designs are implemented using a <span><math><mrow><mn>90</mn><mspace></mspace><mi>nm</mi></mrow></math></span> CMOS process and developed using the Cadence IC Suite for both schematic and layout design. Monte-Carlo analysis, encompassing both process and mismatch, as well as corner analysis, are provided to confirm the robust characteristics of the proposed classifier. Through comparative analysis of post-layout simulation results with an equivalent software-based classifier and related literature, the proper operation of the proposed architecture is confirmed.</p></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":null,"pages":null},"PeriodicalIF":3.0,"publicationDate":"2024-08-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141934695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0