Aeu-International Journal of Electronics and Communications最新文献

{"title":"Miniaturized meandered ring graphene-metal metasurface with wide angle control on the transmitted wave","authors":"Maryam Mokhayer ,&nbsp;Saughar Jarchi ,&nbsp;Reza Faraji-Dana","doi":"10.1016/j.aeue.2024.155566","DOIUrl":"10.1016/j.aeue.2024.155566","url":null,"abstract":"<div><div>In this paper, a miniaturized transmissive metasurface using graphene-metal in the 3.5 THz frequency range is proposed and designed to control the wavefront of the transmitted wave. The designed unit cell has four identical ultra-thin layers. Each layer contains a meandered ring-shaped slot carved in a metal sheet, which is partially filled with four graphene patches in symmetrical places. By employing the meandered shape slots, the lateral dimensions of the unit cells are reduced to 0.19 of the free space wavelength, which, to the best of our knowledge, is the most miniaturized designed structure among the existing transmissive metasurfaces in the literature. Full wave simulations confirmed that without any physical changes and by just altering the spatial distribution of the chemical potential of the graphene patches, wave-front control is achieved. The achievements include beam steering and beam splitting with numerous discrete angles up to 63° and beam focusing with optional focal lengths. It is envisaged that besides 6G wireless telecommunications, this structure could also be beneficial for THz imaging, nano-photonic and opto-electronic devices.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"187 ","pages":"Article 155566"},"PeriodicalIF":3.0,"publicationDate":"2024-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142528471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Creative and accurate method for optimal hardware implementation of neurons and biological cells: Application in FPGA-based implementation of cardiac pacemaker cell","authors":"Gilda Ghanbarpour ,&nbsp;Milad Ghanbarpour ,&nbsp;Pourya Spari","doi":"10.1016/j.aeue.2024.155561","DOIUrl":"10.1016/j.aeue.2024.155561","url":null,"abstract":"<div><div>The sinoatrial (SA) node cells play a vital role as the principal pacemaker in mammalian hearts, generating regular and spontaneous action potentials to regulate the heart’s rhythm. Comprehending the intricate activity of the SA node’s operation necessitates a collection of differential formulas that tackle non-linear functions. The study presents a new technique to improve the digital representation of the SA node cell model, offering benefits such as decreased hardware needs, enhanced processing speed and accuracy, and reduced implementation expenses by transforming the original model’s differential equations into a unified trigonometric function. This transformation significantly simplifies the computational complexity by eliminating the need for multipliers, resulting in a streamlined set of mathematical expressions. The digital implementation of this novel method can be efficiently realized using the Coordinate Rotation Digital Computer (CORDIC) algorithm, which circumvents the necessity for cumbersome mathematical operations. To demonstrate the viability of this approach, the proposed model is successfully synthesized and implemented on a Field-Programmable Gate Array (FPGA). The results of the implementation demonstrate a significant rise in the operating frequency, which is approximately 6.14 times greater than that of the original model. Furthermore, there is a notable 45 percent decrease in power usage. The lowered hardware needs make significant scalability possible, thus allowing for the inclusion of approximately 12 times as many SA node cells on a sole FPGA board in comparison to the original design.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"187 ","pages":"Article 155561"},"PeriodicalIF":3.0,"publicationDate":"2024-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142554458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A low-power quadrature voltage-controlled oscillators with LC emitter degeneration phase shift technique","authors":"Jianxing Lin ,&nbsp;Jinghu Li ,&nbsp;Zhicong Luo ,&nbsp;Mingyan Yu","doi":"10.1016/j.aeue.2024.155557","DOIUrl":"10.1016/j.aeue.2024.155557","url":null,"abstract":"<div><div>This paper introduces a novel phase-shifting technique for quadrature voltage-controlled oscillators (QVCOs) utilizing an LC emitter degeneration architecture. The proposed technique enables a phase shift of up to ±90°in the transconductance of the coupling path while also generating a negative input resistance. This innovative approach avoids phase ambiguity, mitigates the trade-off between phase noise and phase error, and substantially reduces QVCO power consumption. Moreover, compared to conventional capacitance emitter degeneration methods, the LC emitter degeneration structure has a lower equivalent input capacitance, expanding the QVCO’s frequency tuning range. The designed QVCO is implemented using a 180 nm SiGe BiCMOS technology, occupying a compact area of 0.037 mm<span><math><msup><mrow></mrow><mrow><mn>2</mn></mrow></msup></math></span>. Post-layout simulation evaluations under various process, voltage, and temperature (PVT) conditions validate the robustness and reliability of the design. Results indicate a phase noise of 102.7 dBc/Hz at a 1 MHz offset from a 22.1 GHz carrier, a frequency tuning range of 25.2%, a phase error of 0.9°, and a power consumption of 12 mW from a 1.1 V supply, achieving a figure of merit (FoM) of 178.8 dBc/Hz.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"187 ","pages":"Article 155557"},"PeriodicalIF":3.0,"publicationDate":"2024-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142528387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Data-adaptive hybrid control for power quality improvement using H-bridge circuit","authors":"Ravi Kumar Majji ,&nbsp;Tirumalasetty Chiranjeevi ,&nbsp;Radha Kumari N ,&nbsp;G krishnaveni","doi":"10.1016/j.aeue.2024.155560","DOIUrl":"10.1016/j.aeue.2024.155560","url":null,"abstract":"<div><div>The extraction of fundamental current and controlling the H-bridge circuit, called shunt active power filter (SAPF), for power quality support have always been major research concerns. The effectiveness of a SAPF depends on its fundamental component estimation. In this context, empirical mode decomposition (EMD) is applied to SAPF operations due to its effectiveness in complex signal analysis. Being a data-driven, adaptive tool, EMD decomposes the distorted nonlinear signal into signal- and noise-dominated signals, called intrinsic mode functions (IMFs). However, its exploitation has been hindered by its mode mixing issue. As a remedy, a second-order generalized integrator (SOGI) is integrated with the EMD approach to extract the required fundamental active component of distorted load current. Thus, this work investigates the effect of an EMD-based SOGI hybrid control approach in extracting the fundamental active component of distorted load current. The MATLAB/Simulink results demonstrate the effectiveness of the proposed hybrid control strategy for nonlinear load current generated by the diode bridge rectifier. Furthermore, the simulated results are validated through a real-time simulation result using the OPAL-RT OP4510 test bench. Results are analyzed under sinusoidal and distorted voltage scenarios at the point of common coupling. The simulation results showed that the proposed hybrid control approach provides better active filtering efficiency, support for reactive power, and improved total harmonic distortion, which meets the IEEE 1547-2018 standard.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"187 ","pages":"Article 155560"},"PeriodicalIF":3.0,"publicationDate":"2024-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142528475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Charge pump-based PVT-resilient 45 nm CMOS dynamic comparator leveraging high speed and power efficiency","authors":"K. Brindha,&nbsp;J. Manjula","doi":"10.1016/j.aeue.2024.155550","DOIUrl":"10.1016/j.aeue.2024.155550","url":null,"abstract":"<div><div>High-speed, low-power consumption, compact area, and high resolution are critical for analog/mixed signal applications. This article presents a novel design for a dynamic latch comparator that achieves exceptional speed, minimal power consumption, and a significantly reduced die area. The innovative comparator leverages a novel charge shared logic-based reset technique, which enables unparalleled speed and power efficiency. Rigorous simulations and analyses confirm that the delay time is drastically reduced compared to traditional dynamic latched comparators. The results clearly indicate that the proposed design exhibits high tolerance to PVT (process, voltage, and temperature) variations, making it highly suitable for mixed-signal applications. Designed and simulated using advanced 45 nm CMOS technology, the proposed circuit achieves an impressive delay of 18.5 ps and a remarkably low power consumption of 3.66 μW at a 1 V supply voltage and 1 GHz clock frequency.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"187 ","pages":"Article 155550"},"PeriodicalIF":3.0,"publicationDate":"2024-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142528388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A novel semi-angle-based index modulation scheme for MIMO visible light communication","authors":"Manh Le-Tran ,&nbsp;Thai-Hoc Vu","doi":"10.1016/j.aeue.2024.155555","DOIUrl":"10.1016/j.aeue.2024.155555","url":null,"abstract":"<div><div>Visible light communication (VLC) with the use of multiple light-emitting diodes (LEDs) has recently offered extensive indoor coverage for both communication and illumination purposes. Meanwhile, index modulation refers to modulation techniques that use the indices of certain mediums to transmit additional information. The medium can be a time slot, frequency carrier, or especially antenna activation index. In this paper, we present the first attempt at semi-angle-based index modulation for a visible light communication (VLC) system by using LED with different semi-angle values. Instead of using identical semi-angle LEDs, multiple LEDs are divided into several clusters and all LEDs in each cluster have different semi-angle values. Moreover, at any time of transmission, only some clusters are active, and only a single LED of each active cluster is used to convey the pulse amplitude modulation (PAM) signal. We also proposed a minimum mean-squared error (MMSE) based maximum likelihood (ML) detector that performs ML detection on some candidates based on an initial MMSE solution. The simulation results show that the proposed scheme significantly improves the symbol error rate (SER) compared to conventional schemes. Finally, the proposed detector also proves to approach the ML detector performance while still maintaining acceptable complexity cost.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"187 ","pages":"Article 155555"},"PeriodicalIF":3.0,"publicationDate":"2024-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142528474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A simple picowatt 7.6 ppm/°C, 0.029 %/V line sensitivity fully-CMOS voltage reference with DIBL cancelation","authors":"Ali Esmailpoor,&nbsp;Emad Ebrahimi","doi":"10.1016/j.aeue.2024.155558","DOIUrl":"10.1016/j.aeue.2024.155558","url":null,"abstract":"<div><div>In this paper, a 4-transistor sub-one-volt voltage reference with picowatt power consumption is presented. To achieve ultra-low power consumption and low-voltage operation, all transistors are designed to operate in subthreshold region. By proper design of the circuit, DIBL effect is also compensated to enhance temperature coefficient of the circuit and line sensitivity. The proposed circuit consists of only four different transistors (i.e. thick oxide, native V_TH, medium V_TH) in a self-biased scheme such that eliminates the need for any start-up circuit. A prototype of the proposed circuit that generates a 341-mV voltage reference is designed and simulated in a standard 0.18-µm CMOS technology. The proposed reference circuit exhibits an average temperature coefficient of 7.6 ppm/°C across all process corners while the total power consumption is as low as 249 picowatt. The average line sensitivity of the circuit is 0.029 %/V within a wide supply range of 0.6 to 3.3 V. Ultra-low power consumption and line sensitivity, and excellent thermal stability render it ideal for integration into RFID and IoT applications.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"187 ","pages":"Article 155558"},"PeriodicalIF":3.0,"publicationDate":"2024-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142528473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Reconfigurable dielectric resonator antenna and array with frequency and polarization flexibility","authors":"Haoran Xing ,&nbsp;Chaoyi Ma ,&nbsp;Yue Wu ,&nbsp;Mengjun Wang ,&nbsp;Chao Fan ,&nbsp;Hongxing Zheng ,&nbsp;Erping Li","doi":"10.1016/j.aeue.2024.155549","DOIUrl":"10.1016/j.aeue.2024.155549","url":null,"abstract":"<div><div>To implement frequency and polarization hybrid reconfiguration, a 4 × 4 array has been investigated. The radiation elements of the antenna array consist of cylindrical dielectric resonators, Wilkinson power divider, PIN diode, and dielectric substrate. The PIN diode controls the states of each branch in the Wilkinson power divider to achieve frequency and polarization reconfigurability. To verify the feasibility of the design, a fabricated sample of the proposed antenna array has been measured. The results demonstrate that the antenna array can be switched freely between its operating frequencies and polarizations. It operates within a bandwidth of 1.93 to 4.6 GHz for frequency reconfiguration, and three common polarization states—linear polarization, left-handed circular polarization, and right-handed circular polarization—can be continuously tuned from 2.96 to 3.39 GHz.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"187 ","pages":"Article 155549"},"PeriodicalIF":3.0,"publicationDate":"2024-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142446013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A FinFET Based Low-Power Write Enhanced SRAM Cell With Improved Stability","authors":"Atharv Sharma ,&nbsp;Kulbhushan Sharma ,&nbsp;V.K. Tomar ,&nbsp;Ashish Sachdeva","doi":"10.1016/j.aeue.2024.155556","DOIUrl":"10.1016/j.aeue.2024.155556","url":null,"abstract":"<div><div>This work introduces a FinFet based low-power 11T SRAM cell with write enhanced feature, which is considered to meet modern technology requirements due to its distinctive features and performance. The proposed 11T SRAM cell is designed in such a way, so that it reduces the overall power consumption, improving access time, and static noise margin (SNM), especially during the write operation. The proposed 11T SRAM cell is compared with other SRAM cells, including conventional 6T (conv6T), dual pull-up transistor 10T (DPUT10T), dual pull-down transistor 10T (DPDT10T), dual transmission gate 9T (DTG9T), and dual transmission gate 10T (DTG10T), at an equitable standard. The results obtained at the supply voltage of 0.5 V @ 27 °C shows the reduction in leakage power during hold 1 operation by 1.61<span><math><mo>×</mo></math></span>/1.33<span><math><mo>×</mo></math></span>/1.44<span><math><mo>×</mo></math></span>/1.63<span><math><mo>×</mo></math></span>/1.46<span><math><mo>×</mo></math></span>, and reduction in power consumption during read operation by 1.02<span><math><mo>×</mo></math></span>/1.55<span><math><mo>×</mo></math></span>/ 1.01<span><math><mo>×</mo></math></span>/1.81<span><math><mo>×</mo></math></span>/1.97<span><math><mo>×</mo></math></span> in comparison with conv6T/DPUT10T/ DPDT10T/DTG9T/DTG10T, respectively. Write access time is also improved by a factor of 1.67<span><math><mo>×</mo></math></span>/1.71<span><math><mo>×</mo></math></span>/2.59<span><math><mo>×</mo></math></span>/1.45<span><math><mo>×</mo></math></span>/1.97<span><math><mo>×</mo></math></span>, respectively. Additionally, read static noise margin (RSNM) and write static noise margin (WSNM) are improved by 2.03<span><math><mo>×</mo></math></span>/1.01<span><math><mo>×</mo></math></span>/1.65<span><math><mo>×</mo></math></span>/1.54<span><math><mo>×</mo></math></span>/1.43<span><math><mo>×</mo></math></span>, and 1.42<span><math><mo>×</mo></math></span>/1.33<span><math><mo>×</mo></math></span>/1.41<span><math><mo>×</mo></math></span>/1.02<span><math><mo>×</mo></math></span>/1.62<span><math><mo>×</mo></math></span>, respectively. This demonstrates why the proposed low-power 11T SRAM cell is desirable, especially when compared to the other cells under consideration.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"187 ","pages":"Article 155556"},"PeriodicalIF":3.0,"publicationDate":"2024-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142528476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An 11 nW, ＋0.34 °C/−0.38 °C inaccuracy self-biased CMOS temperature sensor at sub-thermal drain voltage","authors":"Bincheng Lei,&nbsp;Yanhan Zeng","doi":"10.1016/j.aeue.2024.155554","DOIUrl":"10.1016/j.aeue.2024.155554","url":null,"abstract":"<div><div>This paper presents a low-power, high-accuracy self-biased full CMOS temperature sensor based on sub-threshold currents at sub-thermal drain voltage. The sensor achieves high accuracy and minimal corner dependence by generating sub-threshold current ratios using NMOS transistors of different sizes operating at sub-thermal drain voltage. The proposed self-biased all-CMOS temperature sensing architecture enhances sensitivity by up to seven times and improves linearity. The overall stability under temperature fluctuations is significantly enhanced by utilizing a substrate diode structure that maintains constant current variation. Additionally, a high-threshold comparator with a fast response compresses the oscillator reset voltage difference, enabling ultra-low power operation. Timing logic control is employed to discard unstable cycle outputs, thereby reducing errors and achieving high-accuracy outputs. Operating at 1 V, the circuit consumes only 11 nW at 27 °C in a 180 nm CMOS process. It achieves a peak-to-peak inaccuracy of ＋0.34 °C/−0.38 °C from −10 to 100 °C after two-point calibration, with a resolution of 40 mK and a resolution FoM as low as 3.7 <span><math><mrow><mtext>pJ</mtext><msup><mrow><mtext>K</mtext></mrow><mrow><mn>2</mn></mrow></msup></mrow></math></span>.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"187 ","pages":"Article 155554"},"PeriodicalIF":3.0,"publicationDate":"2024-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142433715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}