Aeu-International Journal of Electronics and Communications最新文献_第4页

A filtering power divider with high selectivity based on surface acoustic wave resonator 一种基于表面声波谐振器的高选择性滤波功率分配器

IF 3.2 3区计算机科学

Aeu-International Journal of Electronics and Communications Pub Date : 2025-09-04 DOI: 10.1016/j.aeue.2025.156025

Zhongxian Zheng , Jianxing Li , Jitao Chen , Yi Song , Zeting Li , Kai-Da Xu

{"title":"A filtering power divider with high selectivity based on surface acoustic wave resonator","authors":"Zhongxian Zheng , Jianxing Li , Jitao Chen , Yi Song , Zeting Li , Kai-Da Xu","doi":"10.1016/j.aeue.2025.156025","DOIUrl":"10.1016/j.aeue.2025.156025","url":null,"abstract":"<div><div>In this paper, a novel filtering power divider (FPD) based on surface acoustic wave (SAW) resonators is proposed. The proposed FPD integrates the functions of a SAW resonator filtering structure and a power divider, providing highly selective filtering response at two output ports. Microstrip transmission lines, inductors, and SAW resonators are integrated to form the filtering structure that functionally substitutes the quarter-wavelength microstrip line in the traditional Wilkinson power divider. Owing to the symmetry of the circuit topology structure, odd- and even-mode methods are used for analysis. To validate the proposed technique, a high-selectivity FPD based on SAW resonators is designed and fabricated. Measurement results demonstrate an operating bandwidth (return loss > 15 dB) of 989.6–1006.5 MHz with a minimal insertion loss of 1.4 dB. Across the entire passband, the output port isolation exceeds 21 dB, and the shape factor (BW<sub>3dB</sub>/BW<sub>10dB</sub>) is 0.81. The FPD owns advantages of high frequency selectivity and good isolation.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"202 ","pages":"Article 156025"},"PeriodicalIF":3.2,"publicationDate":"2025-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144997630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Third-order single-T and bridged-T LC oscillators and application 三阶单t和桥接t LC振荡器及其应用

IF 3.2 3区计算机科学

Aeu-International Journal of Electronics and Communications Pub Date : 2025-09-03 DOI: 10.1016/j.aeue.2025.155992

B.J. Maundy , A.S. Elwakil , A.A. Nutfaji

引用次数: 0

A -122 dB PSRR curvature-compensated bandgap reference with cross-connected NPN 一个具有交叉连接NPN的-122 dB PSRR曲率补偿带隙基准

IF 3.2 3区计算机科学

Aeu-International Journal of Electronics and Communications Pub Date : 2025-09-03 DOI: 10.1016/j.aeue.2025.156005

Yi Zheng , Zhenjie Yan , Rui Yang , Binhan Zhang , Zhicong Luo , Jinghu Li

{"title":"A -122 dB PSRR curvature-compensated bandgap reference with cross-connected NPN","authors":"Yi Zheng , Zhenjie Yan , Rui Yang , Binhan Zhang , Zhicong Luo , Jinghu Li","doi":"10.1016/j.aeue.2025.156005","DOIUrl":"10.1016/j.aeue.2025.156005","url":null,"abstract":"<div><div>A cross-connected NPN bandgap reference (BGR) circuit with high power supply rejection ratio (PSRR) and low temperature coefficient (TC) is proposed by using curvature-compensated and pre-regulation techniques. Compared with the traditional BGR, it does not require an operational amplifier to clamp the voltage, but uses the voltage feedback of the cross-connected NPN to clamp the voltage, making the structure simpler and eliminating the need to design an operational amplifier. Additionally, by subtracting two nearly identical positive-temperature-coefficient currents, the circuit generates a new current with enhanced curvature, which is then used as a compensating current to reduce the overall temperature coefficient. This compensating current is subsequently scaled by different gain factors to accommodate process-corner variations and serve as a trimming current. Meanwhile, the pre-regulation circuit is respectively adopted to improve PSRR. The proposed BGR circuit is implemented in a 180-nm process, boasting a minimal active area of 0.016 mm<span><math><msup><mrow></mrow><mrow><mn>2</mn></mrow></msup></math></span>. Simulation results show that the BGR has a best TC of 4.13 ppm/<span><math><mrow><msup><mrow></mrow><mrow><mo>°</mo></mrow></msup><mi>C</mi></mrow></math></span> from −40 °C to 125 °C at 3.3 V, a PSRR of −122 dB at low frequencies, and a linear regulation (LR) of 0.0027 mV/V within the supply voltage range of 3.0 V to 3.6 V.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"202 ","pages":"Article 156005"},"PeriodicalIF":3.2,"publicationDate":"2025-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145005227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A modified harmonic minimization scheme for seven-level CHB multilevel inverter with improved voltage harmonic profile and grid code satisfaction 一种改进的七电平CHB多电平逆变器谐波最小化方案，提高了电压谐波分布和电网编码的满意度

IF 3.2 3区计算机科学

Aeu-International Journal of Electronics and Communications Pub Date : 2025-09-03 DOI: 10.1016/j.aeue.2025.156024

Samudra Panda , Sourabh Kundu , Subrata Banerjee

{"title":"A modified harmonic minimization scheme for seven-level CHB multilevel inverter with improved voltage harmonic profile and grid code satisfaction","authors":"Samudra Panda , Sourabh Kundu , Subrata Banerjee","doi":"10.1016/j.aeue.2025.156024","DOIUrl":"10.1016/j.aeue.2025.156024","url":null,"abstract":"<div><div>In this study a modified selective-harmonic-minimization pulse-amplitude-modulation (SHM PAM) scheme is proposed for a 7-level cascaded H-bridge (CHB) multilevel inverter (MLI). The proposed scheme minimizes various lower order harmonics of inverter line voltage, with automatic elimination of the 5th & its higher odd order harmonic components. The modified modulation scheme successfully satisfies six key grid code standards using a 7-level phase voltage waveform, designed based on the proposed angular constraint. The cost function, used to determine the optimized switching angles and per-unit voltages of the proposed voltage pattern, is formulated with a comparatively small number of variables; thereby simplifying and accelerating the overall computational process. This feature facilitates the seamless implementation of the proposed scheme in real-time scenarios. The applicability of the proposed scheme is validated through MATLAB-simulation studies & experimental tests on a 3-phase 7-level CHB MLI laboratory setup under various resistive & inductive loading conditions. Finally, the effectiveness of the proposed scheme is assessed through a comparative study with existing works, considering the number of optimization variables, the number of switching angles, and compliance with grid code standards.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"202 ","pages":"Article 156024"},"PeriodicalIF":3.2,"publicationDate":"2025-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145049733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A parallelized SIW microwave cavity resonator for compact high-Q low phase noise VCOs in 5G and GNSS applications 一种用于5G和GNSS应用中的小型高q低相位噪声压控振荡器的并行SIW微波腔谐振器

IF 3.2 3区计算机科学

Aeu-International Journal of Electronics and Communications Pub Date : 2025-09-02 DOI: 10.1016/j.aeue.2025.156019

Mehran Bakhshi , Seyyed Ali Tabatabaei , Masoud Mollaee , Seyyed Hamed Ayatollahi

{"title":"A parallelized SIW microwave cavity resonator for compact high-Q low phase noise VCOs in 5G and GNSS applications","authors":"Mehran Bakhshi , Seyyed Ali Tabatabaei , Masoud Mollaee , Seyyed Hamed Ayatollahi","doi":"10.1016/j.aeue.2025.156019","DOIUrl":"10.1016/j.aeue.2025.156019","url":null,"abstract":"<div><div>This paper presents a novel method to enhance the quality factor of a simple square resonator designed using Substrate Integrated Waveguide (SIW) technology, while maintaining cost-efficiency and compactness. Our approach leverages parallelized microwave cavities suitable for high-frequency, low phase noise Voltage-Controlled Oscillators (VCOs) used in fifth generation (5G) and Global Navigation Satellite System (GNSS) applications. Modern communication and navigation systems demand precise frequency and timing systems featuring low phase noise performance, compact size, and cost-efficiency. To reduce the need for high manufacturing precision, we incorporated tuning capability into our microwave resonator without compromising performance characteristics. The proposed resonator achieves a competitive loaded quality factor of approximately 150 at 6.8 GHz, with an insertion loss of about 5.5 dB. Its occupied area is about <span><math><mrow><mn>0</mn><mo>.</mo><mn>4</mn><mo>×</mo><mn>0</mn><mo>.</mo><mn>4</mn><mspace></mspace><mrow><mo>(</mo><msub><mrow><mi>λ</mi></mrow><mrow><mn>0</mn></mrow></msub><mo>×</mo><msub><mrow><mi>λ</mi></mrow><mrow><mn>0</mn></mrow></msub><mo>)</mo></mrow></mrow></math></span>, which is an appealing feature for high-frequency applications. Our method enables improved quality factor through increasing the number of resonating microwave layers within the same occupied area. The central resonance frequency can be adjusted via a DC-biasing circuit that controls a varactor capacitor, providing a tuning range of 250 MHz.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"201 ","pages":"Article 156019"},"PeriodicalIF":3.2,"publicationDate":"2025-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144996577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A topology optimization method for designing dielectric microstructures in low-profile and lightweight phased antennas with enhanced scanning capabilities 一种增强扫描能力的低轮廓轻量化相控天线电介质微结构拓扑优化设计方法

IF 3.2 3区计算机科学

Aeu-International Journal of Electronics and Communications Pub Date : 2025-09-01 DOI: 10.1016/j.aeue.2025.156022

Mingyue Zhang , Junwei Zhang , Renjing Gao

{"title":"A topology optimization method for designing dielectric microstructures in low-profile and lightweight phased antennas with enhanced scanning capabilities","authors":"Mingyue Zhang , Junwei Zhang , Renjing Gao","doi":"10.1016/j.aeue.2025.156022","DOIUrl":"10.1016/j.aeue.2025.156022","url":null,"abstract":"<div><div>Stacked phased array antennas play a vital role in modern radar and communication systems due to their capability for wideband and wide-angle beam scanning. However, their application is limited by the fixed dielectric properties of conventional substrates, which restrict bandwidth, scanning performance, and miniaturization. To address this critical challenge, this paper proposes a novel design method that combines topology optimization with 3D printing to generate substrate microstructures with customized dielectric properties. The proposed method includes (1) performance-driven optimization to determine the desired dielectric properties and (2) a topology optimization method based on scattering parameter inversion to realize these properties in manufacturable dielectric structures. A stacked phased array antenna operating in the X-band (8–12 GHz) is designed and fabricated to validate the proposed method. The designed antenna achieves a VSWR < 2 impedance-matching bandwidth covering 8–12 GHz in the normal direction, and maintains VSWR < 2.5 across the same frequency range when scanning up to ± 45° in both the E- and H-planes. In addition, the designed antenna reduces overall weight by 27.5 % while maintaining a low profile of only 8.624 mm. This paper demonstrates a promising pathway to enable the next generation of low-profile, lightweight, and high-performance phased array antennas.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"202 ","pages":"Article 156022"},"PeriodicalIF":3.2,"publicationDate":"2025-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144997628","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A compact frequency-reconfigurable magneto-electric dipole antenna with aperture-coupled excitation for 5G and ISM/WLAN applications 一种紧凑的频率可重构磁电偶极子天线，具有孔径耦合激励，适用于5G和ISM/WLAN应用

IF 3.2 3区计算机科学

Aeu-International Journal of Electronics and Communications Pub Date : 2025-09-01 DOI: 10.1016/j.aeue.2025.156020

Fatemeh Kazemi, Changiz Ghobadi, Javad Nourinia, Majid Shokri

引用次数: 0

A 0.05–20 GHz ultra-wideband CMOS circulator with differential compensation transistors and differential delay lines 一种带差分补偿晶体管和差分延迟线的0.05 ~ 20 GHz超宽带CMOS环行器

IF 3.2 3区计算机科学

Aeu-International Journal of Electronics and Communications Pub Date : 2025-08-31 DOI: 10.1016/j.aeue.2025.156015

Zhengyang Li , Youming Zhang , Fengyi Huang

{"title":"A 0.05–20 GHz ultra-wideband CMOS circulator with differential compensation transistors and differential delay lines","authors":"Zhengyang Li , Youming Zhang , Fengyi Huang","doi":"10.1016/j.aeue.2025.156015","DOIUrl":"10.1016/j.aeue.2025.156015","url":null,"abstract":"<div><div>An ultra-wideband circulator with high TX-to-RX isolation based on an improved structure of sequentially switched delay lines (SSDL) is presented. Novel differential compensation transistors (DCTs) are introduced to cancel the TX signal leakage through the parasitic capacitors of the main switches. To optimize the TX-to-RX isolation over a large bandwidth, a differential delay line (DDL) based on delay compensation technique is proposed to achieve a large delay-bandwidth product (DBW) and a low delay variation (DV). The circulator circuit is implemented in a 40-nm CMOS process with excellent TX-to-RX isolation and a bandwidth substantially larger than the previously reported results, while other performances are comparable to the prior arts. The circulator circuit achieves >24 dB TX-to-RX isolation over the frequency band of 0.05–20 GHz. The TX-to-ANT and ANT-to-RX losses are 4.2–8.3 dB and 4.2–8.7 dB. The circulator exhibits a high TX-induced ANT-RX compression of 10.1–16.8 dBm across the frequency band. The measured input power 1-dB compression points (IP1dB) for TX-to-ANT and ANT-to-RX are 2.1–8.3 dBm and 2.4–7.3 dBm, respectively, with the corresponding input third-order intercept points (IIP3) of 15.6–22.1 dBm and 15.4–22.4 dBm.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"202 ","pages":"Article 156015"},"PeriodicalIF":3.2,"publicationDate":"2025-08-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144997629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Antenna integrated novel metasurface for simultaneous wireless information and power transfer 天线集成新型超表面，实现无线信息和能量同步传输

IF 3.2 3区计算机科学

Aeu-International Journal of Electronics and Communications Pub Date : 2025-08-29 DOI: 10.1016/j.aeue.2025.156018

R. Aneesh Kumar , R. Sethunadh , Chinmoy Saha

{"title":"Antenna integrated novel metasurface for simultaneous wireless information and power transfer","authors":"R. Aneesh Kumar , R. Sethunadh , Chinmoy Saha","doi":"10.1016/j.aeue.2025.156018","DOIUrl":"10.1016/j.aeue.2025.156018","url":null,"abstract":"<div><div>Simultaneous wireless information and power transfer (SWIPT) has recently gained significant attention as promising technology for Internet of Things (IoT). SWIPT enables autonomous IoT nodes with simultaneous energy harvesting (EH) and information transfer (IT) capabilities. For implementation in current compact IoT nodes, the SWIPT system should allow maximum integration of EH and IT chains in small footprint. Proposed work caters to such requirement by establishing planar integration of antenna with metasurface for SWIPT, where metasurface and antenna caters to the EH and IT chain respectively, with high isolation between them. A miniaturized rectifier smaller than the size of the metasurface unit cell is also demonstrated in this work, which allows easy implementation of EH chain. A parasitic slot radiator loaded patch is proposed as antenna element for IT chain, which provides near omni-directional radiation pattern with high gain. The design of the proposed work is carried out at 2.45 GHz frequency. The metasurface is demonstrated in experiment with radiation to AC conversion efficiency close to 90 %, whereas, miniaturized rectifier provides more than 40% rectification efficiency at power as low as -10 dBm. Antenna for IT chain demonstrates peak gain of 7 dBi in experiment with near omni-directional radiation pattern.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"202 ","pages":"Article 156018"},"PeriodicalIF":3.2,"publicationDate":"2025-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145049734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A radiation hardened In-memory computing SRAM for soft error tolerance in safety critical applications 一种用于安全关键应用软容错的抗辐射内存计算SRAM

IF 3.2 3区计算机科学

Aeu-International Journal of Electronics and Communications Pub Date : 2025-08-29 DOI: 10.1016/j.aeue.2025.156017

Biby Joseph, R.K. Kavitha

{"title":"A radiation hardened In-memory computing SRAM for soft error tolerance in safety critical applications","authors":"Biby Joseph, R.K. Kavitha","doi":"10.1016/j.aeue.2025.156017","DOIUrl":"10.1016/j.aeue.2025.156017","url":null,"abstract":"<div><div>In this paper, a radiation-hardened, soft error tolerant 14T SRAM cell (RHBD-IMC14T) featuring in memory computing (IMC) with enhanced reliability is proposed. It has only three sensitive nodes and a separate read path which improves read stability, making the design suitable for IMC operations. It is able to perform OR/NOR, AND/NAND, XOR/XNOR operations, binary content addressable memory (BCAM), and ternary content addressable memory (TCAM) searches efficiently. All the performance comparisons are done in UMC 65 nm technology at 1.2 V, and it achieves 1.2<span><math><mo>×</mo></math></span> , 1.2<span><math><mo>×</mo></math></span> , 1.1<span><math><mo>×</mo></math></span> 1.9<span><math><mo>×</mo></math></span> times higher write stability and 1.2<span><math><mo>×</mo></math></span> , 1.2<span><math><mo>×</mo></math></span> , 6.6<span><math><mo>×</mo></math></span> , 1.4<span><math><mo>×</mo></math></span> times lower power dissipation compared to DICE12T, QUCCE12T, RHSC12T, and RHBD13T, respectively. It also shows a 65% reduction in single event upset probability (P<span><math><msub><mrow></mrow><mrow><mi>S</mi></mrow></msub></math></span>) over DICE12T. The logic operations are performed at 12.52 GHz with an energy consumption of 6.72 fJ/bit. The BCAM and TCAM operations achieve energy efficiencies of 53.53 fJ/bit/search and 51.98 fJ/bit/search at frequencies of 4.06 GHz and 4.26 GHz, respectively. RHBD-IMC14T has critical charge of Qc <span><math><mo>></mo></math></span> 34 fC, ensuring soft error resilience. This work represents one of the earliest efforts to integrate RHBD techniques into IMC capable SRAMs, with robust and energy efficient memory computing for safety critical applications.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"202 ","pages":"Article 156017"},"PeriodicalIF":3.2,"publicationDate":"2025-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145005226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0