Aeu-International Journal of Electronics and Communications最新文献

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High-speed convolutional neural networks using parallel prefix adders 使用并行前缀加法器的高速卷积神经网络
IF 3 3区 计算机科学
Aeu-International Journal of Electronics and Communications Pub Date : 2025-04-07 DOI: 10.1016/j.aeue.2025.155791
Butchi Babu Sarnala, Siva Ramakrishna Pillutla
{"title":"High-speed convolutional neural networks using parallel prefix adders","authors":"Butchi Babu Sarnala,&nbsp;Siva Ramakrishna Pillutla","doi":"10.1016/j.aeue.2025.155791","DOIUrl":"10.1016/j.aeue.2025.155791","url":null,"abstract":"<div><div>Many deep learning applications, particularly image processing, frequently utilize convolutional neural networks (CNNs) due to their remarkable accuracy. However, the heavy computational demands of CNNs pose a challenge for high-speed applications. First, this work introduces a delay efficient hybrid-parallel prefix adder (HPPA) where the total delay is minimized by changing black and gray cell paths. The proposed adder achieves lowest delay compared to the other available PPA adders. It achieves 10.64% reduction in total delay compared to recent PPA Adders. Secondly, we have employed the proposed HPPA adder to obtain a high-speed LeNet CNN architecture. Integration of the proposed hybrid adder into the LeNet CNN architecture significantly reduces the delay in the convolution layer. FPGA implementations of the proposed PPA adder and convolutional layer of LeNet architecture are performed. The proposed PPA adder achieves a 3.05% delay improvement while the critical path delay of the LeNet CNN is reduced by 16.78% compared to the relevant implementations. The implemented LeNet architecture using the proposed delay-efficient PPA adder offers a promising solution for deploying CNNs at high speed applications.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"196 ","pages":"Article 155791"},"PeriodicalIF":3.0,"publicationDate":"2025-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143800512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A review of the state-of-the-art in fractional-order analog filters 分数阶模拟滤波器的最新研究进展
IF 3 3区 计算机科学
Aeu-International Journal of Electronics and Communications Pub Date : 2025-04-04 DOI: 10.1016/j.aeue.2025.155786
Yunus Emre Yokuş , Jaroslav Koton , Roman Sotner , Aslihan Kartci , Umut Engin Ayten
{"title":"A review of the state-of-the-art in fractional-order analog filters","authors":"Yunus Emre Yokuş ,&nbsp;Jaroslav Koton ,&nbsp;Roman Sotner ,&nbsp;Aslihan Kartci ,&nbsp;Umut Engin Ayten","doi":"10.1016/j.aeue.2025.155786","DOIUrl":"10.1016/j.aeue.2025.155786","url":null,"abstract":"<div><div>Today, there is a great tendency toward using fractional calculus to solve engineering problems. The analog filters are one of the fields in which fractional calculus has attracted significant attention. The invention of the fractance device has led to the possibility of exploring analog filtering techniques from a practical perspective, enlarging the horizon to a wider frequency range, with increased robustness to component variation, stability and noise reduction. In addition to the use of fractance device, fractional-order analog filters (FOAFs) can also be realized by integer-order approximation of the <span><math><msup><mrow><mi>s</mi></mrow><mrow><mi>α</mi></mrow></msup></math></span>, optimization and curve fitting techniques (power-law/double-order) methods. The design of FOAFs is thoroughly studied and presented in a manifold of research works, mostly from a theoretic perspective. Most of these papers present the physical realization of the proposed FOAF from a conceptual perspective. This survey paper gives an account of the progress made on the evolution of FOAFs so far and highlights several unresolved problems and issues, including the lack of standardization in design methods, challenges in realizing fractional operators in hardware, complications related to parameter sensitivity and tuning, computational complexity and efficiency, stability analysis and robustness, difficulties in integrating with emerging technologies, and scalability challenges. Furthermore, the supremacies of having a near-ideal FO behavior in filter application are stated and the significant advantages of FOAFs against integer-order analog filters (IOAFs) are emphasized. The paper, thus, presents the current state-of-the art of FOAFs by providing an appraisal of a variety of realizations of FOAFs.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"196 ","pages":"Article 155786"},"PeriodicalIF":3.0,"publicationDate":"2025-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143822356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A compact low phase-noise reconfigurable voltage-controlled oscillator using tunable phase shifter 采用可调移相器的紧凑低相位噪声可重构压控振荡器
IF 3 3区 计算机科学
Aeu-International Journal of Electronics and Communications Pub Date : 2025-04-03 DOI: 10.1016/j.aeue.2025.155773
Upasana Nayak , Prasun Chongder , Animesh Biswas
{"title":"A compact low phase-noise reconfigurable voltage-controlled oscillator using tunable phase shifter","authors":"Upasana Nayak ,&nbsp;Prasun Chongder ,&nbsp;Animesh Biswas","doi":"10.1016/j.aeue.2025.155773","DOIUrl":"10.1016/j.aeue.2025.155773","url":null,"abstract":"<div><div>This article presents a reconfigurable voltage-controlled oscillator (VCO) featuring low phase noise. The design incorporates a highly selective tunable bandpass filter employing two identical stub-loaded open-loop resonators. The filter provides a fixed lower frequency band and a tunable higher band, achieving a total tuning bandwidth of 1.4 GHz. This filter, integrated into the amplifier’s feedback loop as a stabilizing element, ensures that the oscillator operates at a specific frequency within the filter’s frequency range. Reconfigurability is achieved by incorporating a tunable phase-shifter, which introduces additional phase shift to the oscillator circuit. By varying the bias voltage of the phase-shifter’s varactor diodes, the oscillator generates discrete oscillation frequencies (2.74 GHz, 3 GHz, 3.22 GHz, 3.68 GHz, 3.82 GHz and 4.22 GHz) corresponding to the tunable filter’s frequency bands without altering the physical structure of the oscillator. To validate, the proposed design is fabricated. The prototype demonstrates robust performance, achieving measured output powers of −3.97 dBm at 2.74 GHz and −4.37 dBm at 3.68 GHz. Furthermore, the measured phase noise remains low at −129.5 dBc/Hz for 2.74 GHz and −126.9 dBc/Hz for 3.68 GHz at a 1 MHz offset, demonstrating its suitability for RF applications.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"196 ","pages":"Article 155773"},"PeriodicalIF":3.0,"publicationDate":"2025-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143792325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An ultra-broadband polarization conversion metasurface for enhanced stealth and RCS mitigation in MIMO configurations 一种用于MIMO配置中增强隐身性和RCS缓解的超宽带偏振转换超表面
IF 3 3区 计算机科学
Aeu-International Journal of Electronics and Communications Pub Date : 2025-04-01 DOI: 10.1016/j.aeue.2025.155793
Madhusudhan Goud Rangula , Princy Paul , Basudev Majumder , Krishnamoorthy Kandasamy
{"title":"An ultra-broadband polarization conversion metasurface for enhanced stealth and RCS mitigation in MIMO configurations","authors":"Madhusudhan Goud Rangula ,&nbsp;Princy Paul ,&nbsp;Basudev Majumder ,&nbsp;Krishnamoorthy Kandasamy","doi":"10.1016/j.aeue.2025.155793","DOIUrl":"10.1016/j.aeue.2025.155793","url":null,"abstract":"<div><div>A single-layer broadband metasurface for efficient cross-polarization conversion, aiming at improving the stealth performance of a MIMO antenna, is proposed in this work. A low-profile, minimally complex <em>meta</em>-atom and its mirror image are proposed, featuring a diagonal metallic strip and two narrow horizontal edge strips. This configuration achieves more than 90 % polarization conversion efficiency while maintaining an absolute 180-degree phase gradient between the reflected waves of the two <em>meta</em>-atoms. A chessboard metasurface with 10x10 elements, constructed with the proposed <em>meta</em>-atom and mirror image, is integrated with the slot antenna-based MIMO configuration. A slot antenna is orthogonally arranged to form a four-element MIMO configuration, ensuring high isolation exceeding 25 dB between the individual elements. The realized peak gain of this arrangement is 6.95 dBi radiating orthogonally. Monostatic, bistatic, and 3D scattering patterns of a MIMO configuration with and without metasurface are evaluated. Under oblique incidence, the metasurface demonstrates exceptional angular stability, maintaining a minimum RCS reduction of 10 dB for incidence angles up to 60°. The fabricated and optimized prototype exhibits measurement outcomes that closely correspond to the simulation results for normal and oblique incidence scenarios.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"196 ","pages":"Article 155793"},"PeriodicalIF":3.0,"publicationDate":"2025-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143769070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 500MS/s 9-bit two-step SAR ADC with loop-unrolling 一个500MS/s的9位双步SAR ADC,带环展开
IF 3 3区 计算机科学
Aeu-International Journal of Electronics and Communications Pub Date : 2025-04-01 DOI: 10.1016/j.aeue.2025.155783
Xuanhe Zhang, Huijuan Li, Annan Wang, Hui Zeng, Zhang Zhang
{"title":"A 500MS/s 9-bit two-step SAR ADC with loop-unrolling","authors":"Xuanhe Zhang,&nbsp;Huijuan Li,&nbsp;Annan Wang,&nbsp;Hui Zeng,&nbsp;Zhang Zhang","doi":"10.1016/j.aeue.2025.155783","DOIUrl":"10.1016/j.aeue.2025.155783","url":null,"abstract":"<div><div>This paper introduces a passive transfer Two-Step asynchronous loop-unrolling successive approximation register analog-to-digital converter (Two-step LU-SAR ADC). The design employs a loop-unrolling architecture, which traditionally requires calibration operations for comparators that consume time allocated for quantization, thereby reducing speed. To address this issue, the calibration cycle of the second stage is deferred to the subsequent sampling instance by incorporating a pair of switches. This adjustment allows the entire holding time of the second stage to be dedicated to quantization. Furthermore, to overcome the comparison time limitations inherent in SAR ADCs, a novel double-tail comparator is proposed. This comparator initiates its comparison from a mid-voltage state, facilitating a faster determination of outcomes. The proposed ADC is operated at a supply voltage of 1.2 V when simulated using 65-nm CMOS technology. Post-layout simulation results demonstrate that, at a sampling speed of 500 MS/s, the proposed ADC achieves a signal-to-noise and distortion ratio (SNDR) of 53.08 dB, with a power consumption of 3.3 mW, and the figure of merit (FOMw) is 17.98 fJ/conv-step.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"195 ","pages":"Article 155783"},"PeriodicalIF":3.0,"publicationDate":"2025-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143747519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Wideband transmitarray with independent phase/amplitude control for millimeter-wave vehicular sensing and communication 具有独立相位/幅度控制的毫米波车载传感和通信宽带发射阵列
IF 3 3区 计算机科学
Aeu-International Journal of Electronics and Communications Pub Date : 2025-04-01 DOI: 10.1016/j.aeue.2025.155771
Noureddine Melouki, Fahad Ahmed, Peyman PourMohammadi, Hassan Naseri, Tayeb A. Denidni
{"title":"Wideband transmitarray with independent phase/amplitude control for millimeter-wave vehicular sensing and communication","authors":"Noureddine Melouki,&nbsp;Fahad Ahmed,&nbsp;Peyman PourMohammadi,&nbsp;Hassan Naseri,&nbsp;Tayeb A. Denidni","doi":"10.1016/j.aeue.2025.155771","DOIUrl":"10.1016/j.aeue.2025.155771","url":null,"abstract":"<div><div>This paper proposes an innovative multi-bit transmitarray (TA) designed for vehicular sensing applications at Ka-band, featuring 400 unit cells with independent adjustments in both phase and amplitude. The far-field beam-steering mechanism involves calculating phase compensation for each unit cell to redirect the beam toward the desired direction, coupled with a multi-bit amplitude distribution system to reduce side-lobe levels (SLL). A Genetic Algorithm (GA) optimization approach is employed to mitigate gain reduction during amplitude tapering, ensuring robust performance. Thus, the primary contribution of this study is the integration of multi-bit amplitude control with phase manipulation, which collectively enhance beam-steering accuracy and side-lobe suppression, providing a high-performance solution that outperforms traditional designs. Simulation results demonstrate two beam scanning techniques: a phase-only beam steering system with a maximum peak gain of 22.3 dBi and SLLs of −15.7 dB and −14.1 dB for the H- and E-planes, respectively, and an independent phase/amplitude mechanism at angles of 0° and 30°, yielding maximum measured peak gains of 27.2 dBi and 24.5 dBi, respectively. Moreover, the measured side-lobe levels and cross-polarization levels remain below −22.1/−19.4 dB and −44/−35.7 dB, for 0°; −16.3/−19.6 dB and −29.7/−29.05 dB for 30° in H-/E-planes, respectively, making the proposed TA a promising candidate for a high-gain and low SLL mm-Wave vehicular communication system.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"195 ","pages":"Article 155771"},"PeriodicalIF":3.0,"publicationDate":"2025-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143761237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
ASER analysis of fluid antenna systems with rectangular and hexagonal QAM schemes 矩形和六角形QAM流体天线系统的激光激射分析
IF 3 3区 计算机科学
Aeu-International Journal of Electronics and Communications Pub Date : 2025-04-01 DOI: 10.1016/j.aeue.2025.155792
Nuri Kapucu , Mehmet Bilim
{"title":"ASER analysis of fluid antenna systems with rectangular and hexagonal QAM schemes","authors":"Nuri Kapucu ,&nbsp;Mehmet Bilim","doi":"10.1016/j.aeue.2025.155792","DOIUrl":"10.1016/j.aeue.2025.155792","url":null,"abstract":"<div><div>In this work, simple approximate average symbol error rate (ASER) expressions are derived for fluid antenna systems (FAS) with rectangular quadrature amplitude modulation (RQAM) and hexagonal quadrature amplitude modulation (HQAM) schemes over correlated Nakagami-<em>m</em> fading channels between a single-antenna transmitter and a mobile device equipped with FAS. Then, asymptotic expressions are also obtained to explore the diversity order of the considered system. All derived expressions are represented only in terms of rational functions and they can be easily computed without requiring any special function computation or <em>L</em>-fold integration. To obtain ASER expressions and overcome mathematical intractability of ASER integrals, a tight approximation of the Gaussian <em>Q</em> function, <span><math><mrow><mi>Q</mi><mfenced><mrow><mo>·</mo></mrow></mfenced></mrow></math></span>, is used. The performance of FAS-RQAM and FAS-HQAM schemes are compared with the conventional maximum ratio combining (MRC) technique and it is shown that FAS-QAM systems can outperform MRC systems by providing lower ASER values. In addition, the proposed expressions are not only valid for integer values but also valid for non-integer values of fading parameter and antenna size. Results are demonstrated for different configurations of all parameters and modulation schemes and the approximate results show a good fit to the exact results obtained by using exact <span><math><mrow><mi>Q</mi><mfenced><mrow><mo>·</mo></mrow></mfenced></mrow></math></span> in ASER integrals while asymptotic results match well with approximate ones at high signal-to-noise ratio regime. Our approximate results are also found close to the simulation results for both FAS-RQAM and FAS-HQAM schemes.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"196 ","pages":"Article 155792"},"PeriodicalIF":3.0,"publicationDate":"2025-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143792324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A reduced effort design, low power, extremely compact, CMOS ADC based on voltage-to-time converter 一种基于电压-时间转换器的低功耗、极紧凑的CMOS ADC设计
IF 3 3区 计算机科学
Aeu-International Journal of Electronics and Communications Pub Date : 2025-03-31 DOI: 10.1016/j.aeue.2025.155790
Guido Di Patrizio Stanchieri , Orazio Aiello , Andrea De Marcellis
{"title":"A reduced effort design, low power, extremely compact, CMOS ADC based on voltage-to-time converter","authors":"Guido Di Patrizio Stanchieri ,&nbsp;Orazio Aiello ,&nbsp;Andrea De Marcellis","doi":"10.1016/j.aeue.2025.155790","DOIUrl":"10.1016/j.aeue.2025.155790","url":null,"abstract":"<div><div>A low-effort, tiny, low-power, inverter-based Analog-to-Digital Converter (ADC) is proposed in this paper. Based on a Voltage-to-Time Converter (VTC), the architecture requires a minimum design adjustment of the core block to let it work across supply voltages down to 0.3 V. The operation is based on charging and discharging of a timing capacitor, which enables a square wave from a digital counter to be converted from voltage to pulse width as a function of the input voltage signal. In turn, the duty cycle makes counting an additional digital counter driven by a feasible ring oscillator. Post-layout simulations of the designed solution, which relies on TSMC 180 nm standard CMOS technology, show a Si area of 7200 µm<sup>2</sup>, a 6.8 ENOB, a power consumption of 409 nW, and a sample rate of 5 kS/s. These ADC’s extremely low voltage and low power features make it appropriate for energy-harvested Systems-on-Chips (SoCs) in biomedical and Internet of Things (IoT) applications.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"196 ","pages":"Article 155790"},"PeriodicalIF":3.0,"publicationDate":"2025-03-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143776631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Energy efficient high speed dynamic comparators using shared charge logic and auxiliary inverter technique 采用共享电荷逻辑和辅助逆变技术的高能效高速动态比较器
IF 3 3区 计算机科学
Aeu-International Journal of Electronics and Communications Pub Date : 2025-03-30 DOI: 10.1016/j.aeue.2025.155787
Akshay Mann , Neeta Pandey , Maneesha Gupta
{"title":"Energy efficient high speed dynamic comparators using shared charge logic and auxiliary inverter technique","authors":"Akshay Mann ,&nbsp;Neeta Pandey ,&nbsp;Maneesha Gupta","doi":"10.1016/j.aeue.2025.155787","DOIUrl":"10.1016/j.aeue.2025.155787","url":null,"abstract":"<div><div>This work presents two energy efficient, low power dynamic comparators showing an advantage of high speed over the conventional comparator. Both dynamic comparators employ self-cascode technique in the preamplifier stage for improved gain. In the latch stage, the proposed comparator 1 uses shared charge logic technique for low voltage applications while the proposed comparator 2 also combines auxiliary inverters in the later stage in order to improve its speed. The verification of the proposal is done in Cadence Virtuoso simulations at 90 nm CMOS technology node. The proposed comparator 1(2) shows 25.2 (12.6) ps of delay, 24 (39) µW of power and 27.2 (47.4) fJ/conversion of energy. The proposed designs show significant improvements of 80 %, 67 % and 62 % in delay, power and energy respectively. The mismatch analysis for delay, power, energy, offset voltage and kickback noise are also validated using post-layout Monte Carlo analysis is also performed which shows resilience of the proposals.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"195 ","pages":"Article 155787"},"PeriodicalIF":3.0,"publicationDate":"2025-03-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143747518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Optimization algorithm for energy efficiency in vehicular heterogeneous VLC/RF systems based on channel estimation 基于信道估计的车载异构VLC/RF系统能效优化算法
IF 3 3区 计算机科学
Aeu-International Journal of Electronics and Communications Pub Date : 2025-03-27 DOI: 10.1016/j.aeue.2025.155769
Hao Qin , RongRong Yin , MengFa Zhai , KuanKuan Jia , MingQi He , Chun Lang , ShaoYing Ma
{"title":"Optimization algorithm for energy efficiency in vehicular heterogeneous VLC/RF systems based on channel estimation","authors":"Hao Qin ,&nbsp;RongRong Yin ,&nbsp;MengFa Zhai ,&nbsp;KuanKuan Jia ,&nbsp;MingQi He ,&nbsp;Chun Lang ,&nbsp;ShaoYing Ma","doi":"10.1016/j.aeue.2025.155769","DOIUrl":"10.1016/j.aeue.2025.155769","url":null,"abstract":"<div><div>Since Visible Light Communication (VLC) is significantly affected by dynamic channel variations and outdated Channel State Information (CSI), traditional resource allocation methods for heterogeneous VLC/RF systems face challenges in optimizing Energy Efficiency (EE) under such dynamic conditions. To address this issue, this paper proposes a channel estimation method combining Kalman filtering and Minimum Mean Squared Error (MMSE), enabling more accurate estimation of the VLC channel. Based on the channel estimation, we design a Distributed Iterative Joint Channel and Power Optimization (DIJCPO) algorithm for RF/VLC heterogeneous communication systems to maximize EE under dynamic channel conditions. Simulation results demonstrate that the EE performance of the proposed method significantly outperforms that of the comparison algorithms in both curved and straight road scenarios. Moreover, an optimal turning radius further enhances system EE, offering a novel solution for EE optimization in heterogeneous vehicular communication systems.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"195 ","pages":"Article 155769"},"PeriodicalIF":3.0,"publicationDate":"2025-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143738614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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