Aeu-International Journal of Electronics and Communications最新文献_第10页

Programmable CMOS current signal generator for simultaneous multi-sine bioimpedance analysis 可编程CMOS电流信号发生器，用于同时进行多正弦生物阻抗分析

IF 3 3区计算机科学

Aeu-International Journal of Electronics and Communications Pub Date : 2025-02-05 DOI: 10.1016/j.aeue.2025.155701

Israel Corbacho, Juan M. Carrillo, José L. Ausín, Miguel Á. Domínguez, Raquel Pérez-Aloe, J. Francisco Duque-Carrillo

{"title":"Programmable CMOS current signal generator for simultaneous multi-sine bioimpedance analysis","authors":"Israel Corbacho, Juan M. Carrillo, José L. Ausín, Miguel Á. Domínguez, Raquel Pérez-Aloe, J. Francisco Duque-Carrillo","doi":"10.1016/j.aeue.2025.155701","DOIUrl":"10.1016/j.aeue.2025.155701","url":null,"abstract":"<div><div>A fully-differential CMOS current signal generator, suitable for on-chip simultaneous multi-sine bioimpedance spectroscopy, is presented. The proposal is based on generating sinusoidal voltage signals, which are converted into currents and summed in a multiple-input current driver. The oscillators rely on a transconductor-capacitor (<span><math><msub><mrow><mi>G</mi></mrow><mrow><mi>m</mi></mrow></msub></math></span>-<em>C</em>) structure, which allows low-power and wide-frequency-range features. Each input channel of the current driver is a linearized voltage-to-current converter, to deliver a highly-linear multi-sine excitation current. A common-mode feedback (CMFB) network is used to set the DC component of the output voltage, also leading to a high output impedance. The output current can be digitally programmed by means of a 3-bit control signal, which allows measuring a wide range of impedances under test. The circuit has been designed and fabricated in 180 nm CMOS technology to operate with a 1.8-V supply. The output resistance of the current driver has been found to be above 1 M<span><math><mi>Ω</mi></math></span> at low frequencies for the maximum output current of <span><math><mrow><mn>62</mn><mo>.</mo><mn>5</mn><mspace></mspace><mi>μ</mi><mi>A</mi></mrow></math></span> and it is kept higher than approximately 20 k<span><math><mi>Ω</mi></math></span> for a frequency equal to 1 MHz and the same output current level. The output current can be tuned in the range [9.7,62.5] <span><math><mi>μ</mi></math></span>A ensuring that the individual frequency components present a THD lower than <span><math><mo>−</mo></math></span>40 dB.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"192 ","pages":"Article 155701"},"PeriodicalIF":3.0,"publicationDate":"2025-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143372555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Electronically tunable Schmitt trigger with independent TL/TH and output level control using commercially available ICs 电子可调谐施密特触发器与独立的TL/TH和输出电平控制使用市售ic

IF 3 3区计算机科学

Aeu-International Journal of Electronics and Communications Pub Date : 2025-02-04 DOI: 10.1016/j.aeue.2025.155710

Phamorn Silapan, Arisara Luewisutichat, Pawich Choykhuntod, Rapeepan Kaewon

引用次数: 0

Stoch-IMC: A bit-parallel stochastic in-memory computing architecture based on STT-MRAM Stoch-IMC：基于STT-MRAM的位并行随机内存计算架构

IF 3 3区计算机科学

Aeu-International Journal of Electronics and Communications Pub Date : 2025-02-01 DOI: 10.1016/j.aeue.2024.155614

Amir M. Hajisadeghi, Hamid R. Zarandi, Mahmoud Momtazpour

{"title":"Stoch-IMC: A bit-parallel stochastic in-memory computing architecture based on STT-MRAM","authors":"Amir M. Hajisadeghi, Hamid R. Zarandi, Mahmoud Momtazpour","doi":"10.1016/j.aeue.2024.155614","DOIUrl":"10.1016/j.aeue.2024.155614","url":null,"abstract":"<div><div>In-memory computing (IMC) offloads parts of the computations to memory to fulfill the performance and energy demands of applications such as neuromorphic computing, machine learning, and image processing. Fortunately, the main features that stochastic computing (SC) and IMC share, which are low computation complexity and high bit-parallel computation capability, promise great potential for integrating SC and IMC. In this paper, we exploit this potential by using stochastic computation as an approximation method to present effective in-memory computations with a good trade-off among design parameters. To this end, first, commonly used stochastic arithmetic operations of applications are effectively implemented using the primitive logic gates of the IMC method. Next, the in-memory scheduling and mapping of applications are obtained efficiently by a proposed algorithm. This algorithm reduces the computation latency by enabling intra-subarray parallelism while considering the IMC method constraints. Subsequently, a bit-parallel stochastic IMC architecture, Stoch-IMC, is presented that enables bit parallelization of stochastic computations over memory subarrays/banks. To evaluate Stoch-IMC’s effectiveness, various analyses were conducted. Results show average performance improvements of 135.7X and 124.2X across applications compared to binary IMC and related in-memory SC methods, respectively. The results also demonstrate an average energy reduction of 1.5X compared to binary IMC, with limited energy overhead relative to the in-memory SC method. Furthermore, the results reveal average lifetime improvements of 4.9X and 216.3X over binary IMC and in-memory SC methods, respectively, along with high bitflip tolerance.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"190 ","pages":"Article 155614"},"PeriodicalIF":3.0,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143183273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design, analysis and implementation of an optimized cost-effective octagonal patch antenna with UWB characteristics for 5G applications and beyond 设计、分析和实现一种优化的、具有超宽带特性的、具有成本效益的八角形贴片天线，用于5G及以后的应用

IF 3 3区计算机科学

Aeu-International Journal of Electronics and Communications Pub Date : 2025-02-01 DOI: 10.1016/j.aeue.2024.155655

Hind Abbaoui , Salah Eddine EL Aoud , Syed Umaid Ali , Abdelilah Ghammaz , Hassan Belahrach , Saida Ibnyaich

{"title":"Design, analysis and implementation of an optimized cost-effective octagonal patch antenna with UWB characteristics for 5G applications and beyond","authors":"Hind Abbaoui , Salah Eddine EL Aoud , Syed Umaid Ali , Abdelilah Ghammaz , Hassan Belahrach , Saida Ibnyaich","doi":"10.1016/j.aeue.2024.155655","DOIUrl":"10.1016/j.aeue.2024.155655","url":null,"abstract":"<div><div>Microstrip patch antennas have recently garnered significant traction in the wireless communication field due to their cost-effectiveness, low profile, and ease of fabrication on circuit boards. In this context, an ultra-wideband (UWB), optimized, compact, octagonal-shaped microstrip patch antenna (OMPA) designed for multiple 5G, WiFi, and potential 6G uses are presented. The proposed antenna features dimensions of 21 × 23.52 × 1.6 mm<sup>3</sup>, corresponding to electrical measurements of 0.24λ × 0.27λ × 0.026λ. λ represents the free-space wavelength at the resonant frequency of 3.5 GHz. Also, the antenna is printed on a commercially available epoxy substrate with a 4.3 relative permittivity with the ground and radiating patch made of copper of 0.035 mm thickness. In addition, a partial ground structure is used to obtain omnidirectional radiation and miniaturization, while the rectangular slot in the ground greatly enhances the proposed antenna’s bandwidth. After the fabrication and testing of prototypes, the proposed antenna works throughout a frequency range. starting at 3.14 GHz to 13.5 GHz, reaching the entirety of 10 GHz of band with two resonant frequencies of 3.8 GHz and 8 GHz. With its high average efficiency, excellent reflection coefficient profiles and the optimal Voltage Standing Wave Ratio (VSWR) values, the optimized OMPA is a suitable antenna for high data-rate applications in 5G wireless communications operating at sub-6 GHz and sub-7 GHz. This research also highlights the antenna’s potential integration into future 6G standards.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"190 ","pages":"Article 155655"},"PeriodicalIF":3.0,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143183293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Second-generation voltage conveyor-based first-order all-pass filters and application to quadrature sinusoidal oscillator 基于电压传送带的第二代一阶全通滤波器及其在正交正弦振荡器中的应用

IF 3 3区计算机科学

Aeu-International Journal of Electronics and Communications Pub Date : 2025-02-01 DOI: 10.1016/j.aeue.2024.155619

Winai Jaikla , Burin Theppota , Wiset Saksiri , Fabian Khateb , Montree Siripruchyanun

{"title":"Second-generation voltage conveyor-based first-order all-pass filters and application to quadrature sinusoidal oscillator","authors":"Winai Jaikla , Burin Theppota , Wiset Saksiri , Fabian Khateb , Montree Siripruchyanun","doi":"10.1016/j.aeue.2024.155619","DOIUrl":"10.1016/j.aeue.2024.155619","url":null,"abstract":"<div><div>This article describes 2 first-order voltage-mode all-pass filters (APFs) covering leading and lagging phases based on single capacitor and second-generation voltage conveyors (VCIIs). The proposed APFs comprise 2 VCIIs cooperating with 3 resistors and 1 capacitor. The phase angle of the output relative to input signals can be tuned by the single external resistor. Different from previously related works, they use only VCII+ which can be easily realized and less complicated for both integrated circuit architecture and off-the-shelf design. In addition, a 450 mV 1.98 µW VCII based on bulk-driven quasi-floating-gate MOS transistor was developed to be used in this work to achieve ultra low-voltage and low-power consumption. The proposed APFs offer a phase shifting function over a wide range of operating frequency. Its output also provides an accurate sinusoidal signal. The testing results obtained from Cadence Virtuoso System Design Platform simulation are disclosed to investigate different behaviors of the proposed APFs. In addition, the experimental setup using commercially available integrated circuits is shown. From the both results, it is found that they are agreed well with the mentioned anticipations. An application of the proposed APFs in quadrature sinusoidal oscillator is also depicted, it enjoys independent controllability of oscillation condition and oscillation frequency for a wide range of operating frequency with a precise quadrature output signal.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"190 ","pages":"Article 155619"},"PeriodicalIF":3.0,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143183451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design and parametric characterization of CNTFET based stable static random access memory bit-cell for low-power applications 基于CNTFET的低功耗稳定静态随机存取存储器位单元的设计与参数表征

IF 3 3区计算机科学

Aeu-International Journal of Electronics and Communications Pub Date : 2025-02-01 DOI: 10.1016/j.aeue.2024.155642

Divyansh Yadav , Anuja Bhargava , Elangovan Mani , Ashish Sachdeva

{"title":"Design and parametric characterization of CNTFET based stable static random access memory bit-cell for low-power applications","authors":"Divyansh Yadav , Anuja Bhargava , Elangovan Mani , Ashish Sachdeva","doi":"10.1016/j.aeue.2024.155642","DOIUrl":"10.1016/j.aeue.2024.155642","url":null,"abstract":"<div><div>The Carbon Nanotube Field Effect Transistor (CNTFET) is rapidly emerging as an attractive alternative to traditional CMOS transistors. In this work, a stable Feedback Cutting, PPN inverter based 10 transistor (FCPPN10T) Static Random Access Memory (SRAM) bit-cell design based on CNTFETs has been designed for low-power operations. The proposed cell has been tested for key parametric variation of CNTFET transistors such as chiral vector, pitch, number of carbon nonotubes, dielectric constant, and oxide thickness. The proposed FCPPN10T SRAM cell improves read/write static noise margin by 1.98<span><math><mo>×</mo></math></span>/ 1.132<span><math><mo>×</mo></math></span>, respectively, at 0.3 V compared to conventional 6T SRAM that uses similar CNTFET parameters. The read/write delay of proposed FCPPN10T is higher by 1.03<span><math><mo>×</mo></math></span>/ 1.24<span><math><mo>×</mo></math></span>, respectively, at 0.3 V compared to conventional 6T SRAM. The leakage power of proposed design is improved by 4.118<span><math><mo>×</mo></math></span> compared to conventional 6T. The proposed design parameters are also compared with three pre-proposed SRAM bit-cells. The simulation is performed with the Cadence Virtuoso using the Stanford University 32 nm CNTFET Verilog model.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"190 ","pages":"Article 155642"},"PeriodicalIF":3.0,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143183575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Ku-Band dual-sense CP array antenna with polarization converter element 一种带极化变换器元件的ku波段双感CP阵列天线

IF 3 3区计算机科学

Aeu-International Journal of Electronics and Communications Pub Date : 2025-02-01 DOI: 10.1016/j.aeue.2024.155637

Mir Hadi Teimouri, Changiz Ghobadi, Javad Nourinia

引用次数: 0

Substrate integrated waveguide bandpass filter with wide upper stopband 宽上阻带的基板集成波导带通滤波器

IF 3 3区计算机科学

Aeu-International Journal of Electronics and Communications Pub Date : 2025-02-01 DOI: 10.1016/j.aeue.2025.155663

Ajay Gupta, Arani Ali Khan

{"title":"Substrate integrated waveguide bandpass filter with wide upper stopband","authors":"Ajay Gupta, Arani Ali Khan","doi":"10.1016/j.aeue.2025.155663","DOIUrl":"10.1016/j.aeue.2025.155663","url":null,"abstract":"<div><div>This communication presents the design of a Substrate Integrated Waveguide (SIW) Bandpass Filter (BPF) with wide stopband. The BPF is centered at 3.5 GHz with 0.5 dB equal ripple bandwidth of 4 % and offering a stopband extended up to 40 GHz. The FBW is so chosen that the variation of insertion loss remains within 1 dB over the 3.4 GHz – 3.6 GHz communication band. The proposed vertical integration uses the coupling through rectangular slots on the common plane of two SIW resonators. The slots are positioned to obtain required coupling in the TE<sub>110</sub> mode whereas at other higher order modes, couplings are minimum resulting a wide stopband. In measurement, the BPF offers minimum insertion loss of 2.55 dB at the center frequency of <em>f</em><sub>0</sub> = 3.49 GHz and over 3.42 GHz – 3.59 GHz, it remains better than 3.55 dB. Over the mentioned frequency band, the measured return loss is better than 15 dB. The out of band rejection is at least 50 dB at (<em>f</em><sub>0</sub> + 0.22) GHz and (<em>f</em><sub>0</sub> – 0.2) GHz whereas in the upper stopband, minimum suppression is 40 dB over 3.7 GHz – 20 GHz and remains better than 30 dB up to 40 GHz.</div><div><em>Index Terms</em>— Substrate Integrated Waveguide (SIW), Bandpass filter (BPF), harmonics.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"191 ","pages":"Article 155663"},"PeriodicalIF":3.0,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143285385","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Compact 2T1C and Cryo-2T1C CMOS Memristor Emulator for Neuromorphic and Quantum Computing 用于神经形态和量子计算的紧凑2T1C和Cryo-2T1C CMOS忆阻器仿真器

IF 3 3区计算机科学

Aeu-International Journal of Electronics and Communications Pub Date : 2025-02-01 DOI: 10.1016/j.aeue.2025.155683

Sara Paul, Digambar Laxman Bhole, R.K. Kavitha

{"title":"A Compact 2T1C and Cryo-2T1C CMOS Memristor Emulator for Neuromorphic and Quantum Computing","authors":"Sara Paul, Digambar Laxman Bhole, R.K. Kavitha","doi":"10.1016/j.aeue.2025.155683","DOIUrl":"10.1016/j.aeue.2025.155683","url":null,"abstract":"<div><div>In this a new 2T1C (2 Transistors and 1 Capacitor) memristor emulator design which is compact and energy efficient is proposed. It achieves a maximum operating frequency of 150 MHz. The simple circuit design leads to a power consumption of <span><math><mrow><mn>13</mn><mo>.</mo><mn>1</mn><mspace></mspace><mi>μ</mi><mi>W</mi></mrow></math></span> and occupies a minimal area of <span><math><mrow><mn>1</mn><mo>.</mo><mn>25</mn><mspace></mspace><mi>μ</mi><msup><mrow><mi>m</mi></mrow><mrow><mn>2</mn></mrow></msup></mrow></math></span> at room temperature (RT). The chip area and power consumption of 2T1C memristor emulator are 4 and 74 times lesser than the PMME/NMME memristor emulator respectively. In addition to that, a Cryo-2T1C memristor emulator is proposed and its performance is analysed at cryogenic temperature (4.2 K). The Cryo-2T1C could be considered as the first Cryo-CMOS memristor emulator, which has better memristive characteristics at 4.2 K. The Cryo-2T1C memristor has a power consumption of <span><math><mrow><mn>47</mn><mi>μ</mi></mrow></math></span>W and occupies an area of <span><math><mrow><mn>3</mn><mo>.</mo><mn>1</mn><mspace></mspace><mi>μ</mi><msup><mrow><mi>m</mi></mrow><mrow><mn>2</mn></mrow></msup></mrow></math></span> and also operates at a frequency of 150 MHz. To ensure the correctness of memristive characteristics, the proposed designs are verified at various frequencies and voltage levels at RT and 4.2 K in UMC 65 nm process technology. The proposed 2T1C and Cryo-2T1C emulator designs are able to retain the Pinched Hysteresis Loop (PHL) for different process variations and mismatches in both RT and 4.2 K. Hence, the proposed designs are suitable for low power and high frequency applications.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"191 ","pages":"Article 155683"},"PeriodicalIF":3.0,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143285390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A high accuracy bandgap reference with adaptive mechanical stress compensation 具有自适应机械应力补偿的高精度带隙基准

IF 3 3区计算机科学

Aeu-International Journal of Electronics and Communications Pub Date : 2025-02-01 DOI: 10.1016/j.aeue.2025.155674

Pengda Qu , Zhiming Xiao , Yue Zhao , Khalil Yousef

{"title":"A high accuracy bandgap reference with adaptive mechanical stress compensation","authors":"Pengda Qu , Zhiming Xiao , Yue Zhao , Khalil Yousef","doi":"10.1016/j.aeue.2025.155674","DOIUrl":"10.1016/j.aeue.2025.155674","url":null,"abstract":"<div><div>Mechanical stress due to packaging and soldering process is a random non-ideal factor which has been annoying the design of high accuracy analog ICs for a long time. Soldering and mechanical stress would make trimming meaningless after packaging in bandgap reference (BGR) circuits. This paper proposes adaptive stress compensation technique for high accuracy BGR design. This is implemented by feeding the bandgap circuit with a compensation current extracted from the difference of the base-emitter junctions’ voltage (<span><math><msub><mrow><mi>V</mi></mrow><mrow><mi>B</mi><mi>E</mi></mrow></msub></math></span>) variations between NPN and PNP bipolar transistors experiencing the same stress. It was found that the temperature coefficient variations caused by soldering can be enhanced by a factor of 45.3%. The measured temperature coefficient of the reference voltage before soldering is 7.02 ppm/°C, while it is 24.73 ppm/°C after soldering. The proposed compensation technique reduced the measured reference voltage temperature coefficient to 15.03 ppm/°C.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"191 ","pages":"Article 155674"},"PeriodicalIF":3.0,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143285783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0