Aeu-International Journal of Electronics and Communications最新文献

{"title":"Modeling and optimization of power distribution network using response surface methodology for power integrity analysis","authors":"Aprajita Bera ,&nbsp;Sudhakar Mande","doi":"10.1016/j.aeue.2024.155644","DOIUrl":"10.1016/j.aeue.2024.155644","url":null,"abstract":"<div><div>Complex semiconductor packages face Power Integrity (PI) issues due to high speed operation and denser geometries. DC and AC analysis of the power distribution network is critical to ensure that the electrical response parameters are within the specified tolerance range. Failing this can lead to device malfunction and therefore require multiple design re-spins. This paper proposes a novel methodology for predictive analysis of power integrity (PI) performance of power distribution networks (PDN). In the proposed technique, Plackett Burman Design of Experiments (PB-DoE) and Response Surface Modeling (RSM) are used to develop an empirical model for predicting response parameters such as DC drop voltage, current density and impedance of the PDN at the early stage of the design cycle. The empirical model developed in this work is validated using Mentor Graphics HyperLynx PI tool for the developed test case with identical input design parameters. The response parameters obtained from the analytical model and the simulator give close agreement with an error of 6%. The process improvement optimization method is successfully implemented using the response surface model to improve the performance of the system. The suitability of the proposed technique is verified over the frequency range of 1 MHz to 1 GHz.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"190 ","pages":"Article 155644"},"PeriodicalIF":3.0,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143183579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An efficient ternary multiplier for enhanced on-chip AI wearable systems using graphene nanoribbon field-effect transistors","authors":"Jialing Li ,&nbsp;Zhongjian Tang ,&nbsp;Haitham A. Mahmoud","doi":"10.1016/j.aeue.2024.155658","DOIUrl":"10.1016/j.aeue.2024.155658","url":null,"abstract":"<div><div>Enhanced on-chip AI wearable systems are transforming the interaction between individuals and technology, facilitating the development of smarter and more responsive devices that integrate seamlessly into everyday life. As the demand for such advanced systems increases, the necessity for energy-efficient circuits that provide extended battery life alongside high-performance processing becomes paramount. Within this framework, the graphene nanoribbon field-effect transistor (GNRFET) presents a promising solution, particularly due to its capability for ternary processing, which significantly enhances response speed, reduces power dissipation, and improves area efficiency.This paper presents an innovative ternary multiplier (TMUL) utilizing GNRFET technology, specifically designed to achieve reduced propagation delay, lower power consumption, and increased robustness against process variations, all while minimizing the transistor count. The proposed architecture incorporates a single transistor within the logic pathways leading to the outputs, integrates a greater number of high-threshold voltage (<em>V_th</em>) devices, and employs unary operators. These characteristics collectively advance the design objectives.The efficiency of the proposed TMUL is evaluated in comparison to seven contemporary TMUL circuits, employing a 32-nm GNRFET technology node with a supply voltage of 0.9 V. Remarkably, our design exhibits improvements of at least 8.98 % in delay, 2.22 % in power consumption, and 40.88 % in energy efficiency. Further performance assessment through Monte Carlo simulations confirms the superiority of the proposed design, underscoring its enhanced reliability amidst process variations and its minimal variance in energy consumption. By integrating the proposed single-trit TMUL to 3-trit TMUL, the projected circuit requires 1139 GNRFETs, with low power consumption and high speed operation.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"191 ","pages":"Article 155658"},"PeriodicalIF":3.0,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143285374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An 8–18 GHz ultrawideband gap waveguide folded bandpass filter for radar applications","authors":"Abdullah J. Alazemi ,&nbsp;Davood Zarifi ,&nbsp;Ali Farahbakhsh","doi":"10.1016/j.aeue.2025.155692","DOIUrl":"10.1016/j.aeue.2025.155692","url":null,"abstract":"<div><div>The present work introduces a compact ultrawideband filter based on folded ridge gap waveguide. The design and fabrication of a ninth-order bandpass filter demonstrates its capabilities, achieving a 75 % fractional bandwidth, a return loss (RL) of 17.6 dB, and an insertion loss (IL) of 0.52 dB within the 8.22 to 18.15 GHz frequency range. The fabricated prototype shows excellent agreement between simulations and measurements. The designed filter offers reduced size and wider frequency bandwidth in comparison with similar bandpass filters based on gap waveguide and exhibits significant potential for X- and Ku-bands radar systems.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"191 ","pages":"Article 155692"},"PeriodicalIF":3.0,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143285387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Microwave bandpass filter based on modified square ring and dumbbell shaped resonator for UWB applications","authors":"Partha Protim Kalita ,&nbsp;Gouree Shankar Das ,&nbsp;Akash Buragohain ,&nbsp;Yatish Beria ,&nbsp;Trishna Doloi","doi":"10.1016/j.aeue.2025.155682","DOIUrl":"10.1016/j.aeue.2025.155682","url":null,"abstract":"<div><div>An ultra-wideband (UWB) microstrip bandpass filter is designed and developed on a low-cost FR4 substrate with a dimension of <em>1.15λ_g</em> × <em>0.38λ_g</em> × <em>0.06λ_g</em>. The filter has been designed using ANSYS High Frequency Structure Simulator (HFSS) electromagnetic (EM) software. It is based on a modified stepped impedance square ring resonator excited by quarter wavelength interdigital parallel coupled microstrip lines (PCML) on both ends to obtain UWB performance. Two dumbbell-shaped resonators and rectangular defected ground structures (DGS) are introduced to get a sharper transition from passband to stopband and to minimize the insertion loss respectively. Due to the symmetric structure of the filter, it is analyzed using odd–even mode analysis to find the resonant mode. To validate the EM simulated results, a lumped element equivalent circuit has been proposed. Further, the fabricated filter has been tested using Vector Network Analyzer (VNA) and the passband of the filter is found to be from 2.98 GHz to 9.59 GHz with a fractional bandwidth of 105.2 % and a minimum insertion loss of 0.38 dB. High return loss of −20.4 dB is observed with a group delay variation of 0.36 ns throughout the passband. The proposed filter is suitable for UWB applications like high-speed wireless communication and radar applications.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"191 ","pages":"Article 155682"},"PeriodicalIF":3.0,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143285782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A novel beamforming method for array antennas integrating Extended maximum power transfer efficiency and Genetic algorithm","authors":"Shihang Song ,&nbsp;Guowen Ding ,&nbsp;Xin-Yao Luo ,&nbsp;Shen-Yun Wang","doi":"10.1016/j.aeue.2025.155676","DOIUrl":"10.1016/j.aeue.2025.155676","url":null,"abstract":"<div><div>This paper presents a novel beamforming method for array antennas that integrates the Extended Maximum Power Transfer Efficiency (EMMPTE) technique with the Genetic Algorithm (GA). This approach achieves both maximum power transfer and significant precision in energy distribution across multiple beams. The process starts with extracting the far-field electric field parameters of the antenna array. The EMMPTE technique is then used to maximize efficiency in the target beam direction. To ensure accurate energy control between beams, specific constraints are introduced, and the GA is employed to handle the complex requirements of beamforming, efficiency optimization, and energy distribution control simultaneously. This method’s innovation lies in its dual ability to maximize power transfer while precisely controlling energy distribution under complex constraints. The method was validated using a dual-substrate linearly polarized patch antenna array for the 5G frequency band (3.3–3.6 GHz). Experiments with dual-beam and triple-beam configurations showed that the method allows precise control of individual beams in multi-beam scenarios. The simulation results closely match experimental measurements, confirming the method’s effectiveness.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"191 ","pages":"Article 155676"},"PeriodicalIF":3.0,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143285376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"CNTFET based leakage control static approximate full adder circuit for high performance multimedia applications","authors":"Sagar Juneja ,&nbsp;Kulbhushan Sharma","doi":"10.1016/j.aeue.2024.155626","DOIUrl":"10.1016/j.aeue.2024.155626","url":null,"abstract":"<div><div>The need for implementing fast and low-power digital circuits for high-performance multimedia applications running on portable devices demands major improvements in the design of full adder (FA) circuits, which form the fundamental building block of a digital system. In this work, a novel design of a FA circuit has been reported using a 32 nm CNTFET device to meet and improve the three design criteria of a FA, including speed, power consumption, and transistor count. Leveraging the benefits of approximate computing for multimedia applications, the proposed FA circuit has been implemented by modifying the 24-transitor conventional mirror adder circuit and using the leakage control transistor-based approach for minimizing the leakage power. This 11-transitor leakage control static approximate full adder (11T-LCSAFA) produces three erroneous outputs, and it has a power dissipation of 3.132 nW, propagation delay of 3.743 ps, and PDP of 11.72 x <span><math><msup><mrow><mn>10</mn></mrow><mrow><mo>-</mo><mn>21</mn></mrow></msup></math></span> J when operating at a voltage of 500 mV. Furthermore, the proposed 11T-LCSAFA has been used for implementing a 4-bit ripple carry adder (RCA) circuit to perform a multistage analysis. The implemented RCA has a maximum propagation delay of 39.929 ps, power dissipation of 23.37 nW, and PDP of 933 x <span><math><msup><mrow><mn>10</mn></mrow><mrow><mo>-</mo><mn>21</mn></mrow></msup></math></span> J.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"190 ","pages":"Article 155626"},"PeriodicalIF":3.0,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143183271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Benchmark antenna designs via wind driven optimization with dynamic control parameters","authors":"Xingning Jia,&nbsp;Siye Wu,&nbsp;Liao Ma","doi":"10.1016/j.aeue.2024.155653","DOIUrl":"10.1016/j.aeue.2024.155653","url":null,"abstract":"<div><div>An approach to accelerating the convergence of the wind driven optimization (WDO) is proposed based on a novel Taguchi-based dynamic control parameter (CP) identification method. To find the best CP combinations with different numbers of fitness evaluations, the Taguchi method is used, and the fitted dynamic CP functions are determined to represent the variation of each CP. Furthermore, an extra velocity update strategy is proposed, which integrates information from both the personal best and the global best to enhance the exploitation of WDO. The proposed algorithm is validated by nine benchmarks involving four functions and five antenna designs. Additionally, its optimization performance is compared with that of state-of-the-art meta-heuristic algorithms. The results demonstrate the effectiveness of this method in improving the convergence speed of WDO.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"190 ","pages":"Article 155653"},"PeriodicalIF":3.0,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143183296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Experimental validation of a high-frequency memristor emulator based on CCCCTA framework and its application in chaos circuit","authors":"Prashant Kumar ,&nbsp;Basit Shafat Makhdoomi ,&nbsp;Jagveer Singh Verma ,&nbsp;Shweta Sonwani ,&nbsp;Rahul Ranjan ,&nbsp;Rajeev Kumar Ranjan","doi":"10.1016/j.aeue.2024.155624","DOIUrl":"10.1016/j.aeue.2024.155624","url":null,"abstract":"<div><div>In this article, we introduce a Memristor Emulator model employing a single analog building block i.e., the Current Controlled Current Conveyor Transconductance Amplifier (CCCCTA), along with two resistors and one capacitor. The proposed memristor emulator operates up to 1 MHz and spans over a chip area of <span><math><mrow><mn>38</mn><mo>.</mo><mn>23</mn><mspace></mspace><mi>μ</mi><mi>m</mi><mo>×</mo><mn>48</mn><mo>.</mo><mn>34</mn><mspace></mspace><mi>μ</mi><mi>m</mi></mrow></math></span>. In addition, by using a simple switch connection, the proposed emulator circuit can be configured in both incremental as well as decremental configurations. The simulation results are based on a <span><math><mo>±</mo></math></span>1.1 V power supply and have been carried out on a 180 nm CMOS technology node. The results perfectly corroborate the theoretical propositions. Besides, the design incurs a power consumption of only 2.2 mW. The performance measures of the proposed memristor model have been assessed using Monte Carlo simulations. In addition, we have also verified the theoretical findings experimentally using off-the-shelf integrated circuits. The non-ideal analysis and post-layout simulations have been added to show the effects of the parasitic resistances and capacitances on the proposed memristor emulator. The effect of noise at the input has been incorporated using computer simulation to further assess the robust nature of the design. At last, we show the applicability of the proposed emulator circuit in generating chaos as well as amoeba’s adaptive behavior.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"190 ","pages":"Article 155624"},"PeriodicalIF":3.0,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143183452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Temperature-less-sensitive trans-impedance amplifier with background light cancellation loop","authors":"Asmaa Gamal Tantawy ,&nbsp;Ahmed Wahba ,&nbsp;Hesham F.A. Hamed ,&nbsp;Ahmed Reda Mohamed","doi":"10.1016/j.aeue.2024.155625","DOIUrl":"10.1016/j.aeue.2024.155625","url":null,"abstract":"<div><div>A temperature-less-sensitive photoplethysmography (PPG) sensor integrated circuit with a background light loop for monitoring vital signs is proposed. The proposed PPG sensor contains a low-power trans-impedance amplifier (TIA) with a background light (BGL) loop and a temperature sensing circuit (TSC). The background light loop assists in rejecting the DC photocurrent up to 15 <span><math><mi>μ</mi></math></span>A, improving the total harmonic distortion (THD) by 15.7X. Meanwhile, the TSC improves the TIA’s temperature robustness by more than 14X over a wide range of temperature variations from <span><math><mrow><mo>−</mo><mn>40</mn><mspace></mspace><mo>°</mo><mi>C</mi></mrow></math></span> to <span><math><mrow><mn>85</mn><mspace></mspace><mo>°</mo><mi>C</mi></mrow></math></span>. The proposed circuit is designed and analyzed using the signal-flow graph (SFG) strategy to prove the functionality’s performance. In TSMC 0.18 <span><math><mi>μ</mi></math></span>m CMOS technology, the circuit is simulated and occupies a silicon area of 320 <span><math><mi>μ</mi></math></span>m x 345 <span><math><mi>μ</mi></math></span>m, providing seamless integration with the wearable devices. The pre- and post-layout simulation results are matched and consistent with a relative error less than 1 %. Statistical analysis based on Monte-Carlo (MC) and process–voltage–temperature variations (PVTs) have been executed to guarantee the well-functionality performance throughout future manufacture. The post-layout simulation results indicate the midband gain reaches 115 dB and the power consumption is 27 <span><math><mi>μ</mi></math></span>W with a single power supply of 1.8 V. Furthermore, the high-pass corner frequency, the low-pass corner frequency, and the total input referred noise reach 60 mHz, 112 Hz, and 2 pArms, respectively. Out of the figure of merits (<span><math><mrow><mi>F</mi><mi>O</mi><mi>M</mi><mi>s</mi></mrow></math></span>), the functionality performance of the proposed circuit has been verified with a perfusion index (PI) of 3.3 % and performs superior to the prior arts.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"190 ","pages":"Article 155625"},"PeriodicalIF":3.0,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143183576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Multiband antenna design with a defected ground structure for 5G and X-band applications","authors":"Hakan Kisioglu","doi":"10.1016/j.aeue.2024.155651","DOIUrl":"10.1016/j.aeue.2024.155651","url":null,"abstract":"<div><div>The rapid advancement of new generation wireless communication systems has led to an increased demand for multiband antennas, which are capable of functioning across multiple frequency bands. This paper presents the design of a multiband antenna with defective ground structure for 5G and X-Band applications. The proposed antenna has overall dimensions (0.35λo × 0.35λo × 0.012λo) with respect to the lowest resonant frequency and is designed with an FR-4 substrate material. The proposed design enables the antenna to achieve relatively high gains in six different frequency bands, 2.02 dBi, 3.1 dBi, 5.37 dBi, 2.99 dBi, 3.11 dBi, and 6.48 dBi at 2.33 GHz, 3.3 GHz, 5.03 GHz, 6.84 GHz, 8.12 GHz, and 9.75 GHz, respectively. The proposed antenna exhibited −10 dB impedance bandwidths of 4.72 % (2.29–2.365 GHz), 4.24 % (3.24–3.37 GHz), 3.38 % (4.97–5.15 GHz), 3.95 % (6.69–6.96 GHz), 3.94 % (7.98–8.29 GHz), and 6.67 % (9.45–10.08 GHz) across diverse frequency bands. The antenna structure was fabricated and measurement results were obtained. A satisfactory agreement was observed between the simulation and the corresponding measurement results. The detailed performance analysis of the proposed antenna, together with measured and simulated results, shows that it is suitable for 5G and X band applications.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"190 ","pages":"Article 155651"},"PeriodicalIF":3.0,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143183581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}