Aeu-International Journal of Electronics and Communications最新文献_第9页

A low loss tri-band negative group delay circuit with resistors 带电阻的低损耗三带负群延迟电路

IF 3.2 3区计算机科学

Aeu-International Journal of Electronics and Communications Pub Date : 2026-02-01 Epub Date: 2025-11-25 DOI: 10.1016/j.aeue.2025.156144

Yuwei Meng, Zhenping Lan

引用次数: 0

A multi-harmonic class-D FSK power and data transmitter with enhanced load power delivery and high data rate to carrier frequency ratio for biomedical implants 一种用于生物医学植入物的多谐波d类FSK功率和数据传输器，具有增强的负载功率传输和高数据速率与载频比

IF 3.2 3区计算机科学

Aeu-International Journal of Electronics and Communications Pub Date : 2026-02-01 Epub Date: 2025-12-02 DOI: 10.1016/j.aeue.2025.156161

Akbar Asgharzadeh Bonab , Khashayar Dehghan , Jalil Mazloum

{"title":"A multi-harmonic class-D FSK power and data transmitter with enhanced load power delivery and high data rate to carrier frequency ratio for biomedical implants","authors":"Akbar Asgharzadeh Bonab , Khashayar Dehghan , Jalil Mazloum","doi":"10.1016/j.aeue.2025.156161","DOIUrl":"10.1016/j.aeue.2025.156161","url":null,"abstract":"<div><div>This paper presents a novel wireless power transfer and data telemetry circuit for biomedical implants that enhances both data rate and power delivery to the load. The proposed system employs a multi-coil, single-carrier frequency shift keying (FSK) transmitter architecture, where power and data are simultaneously transmitted via three magnetically coupled resonant links. These links are excited by a class-D amplifier operating at the first, third, and ninth harmonics of a base frequency. Bit encoding is performed by switching between two resonant modes: when the data bit is “0,” the system transmits at the base frequency f<sub>0</sub>; when the bit is “1,” it switches to 3f<sub>0</sub>. This design leverages first, third, and ninth harmonic resonance to improve power delivered to the load and simplify modulation circuitry. The system has an ability to achieve a data rate equal to f<sub>0</sub>, resulting in a data-rate-to-f<sub>0</sub> ratio of 100 %. A proof-of-concept prototype was implemented on a printed circuit board and evaluated at operating frequencies of 298 kHz and 894 kHz. The transmitter delivers 1.1 W to the load with a power transfer efficiency of approximately 42 %, achieving a data rate of 0.298 Mbps and a bit error rate (BER) <span><math><mrow><mn>5.33</mn><mo>×</mo><msup><mrow><mn>10</mn></mrow><mrow><mo>-</mo><mn>6</mn></mrow></msup></mrow></math></span>.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"205 ","pages":"Article 156161"},"PeriodicalIF":3.2,"publicationDate":"2026-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145684710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Spiking neural network with 1T-1R RRAM synapses and CMOS LIF neurons for in-situ learning and pattern recognition 基于1T-1R RRAM突触和CMOS LIF神经元的脉冲神经网络用于原位学习和模式识别

IF 3.2 3区计算机科学

Aeu-International Journal of Electronics and Communications Pub Date : 2026-02-01 Epub Date: 2025-11-24 DOI: 10.1016/j.aeue.2025.156145

Nivetha T. , Bindu B. , Noor Ain Kamsani

{"title":"Spiking neural network with 1T-1R RRAM synapses and CMOS LIF neurons for in-situ learning and pattern recognition","authors":"Nivetha T. , Bindu B. , Noor Ain Kamsani","doi":"10.1016/j.aeue.2025.156145","DOIUrl":"10.1016/j.aeue.2025.156145","url":null,"abstract":"<div><div>The neuromorphic computation has gained attention over traditional computing techniques due to its low power consumption, real-time processing and adaptability. The spiking neural networks (SNN) are event-based which process information as spikes to provide high energy efficiency and fast computation. In this article, a novel SNN with CMOS neuron and resistive random access memory (RRAM) synapses is implemented for pattern recognition. The RRAM synapses exhibit synaptic plasticity suitable for in-memory computations. A computationally efficient CMOS based leaky integrate and fire (LIF) neuron model is implemented to handle the data-driven applications effectively. The SNN contains the forward and feedback mode operation. In the forward mode, the input pre-spikes with ON-bit and OFF-bit frequencies corresponding to the binary pixel intensities of the image are applied to the RRAM synaptic array. The CMOS LIF neuron integrate these spikes from synapses and produce the post-spikes. In the feedback mode, these post-spikes are given to the sense line and the synaptic weights get modified using spike time-dependent plasticity (STDP) learning mechanism. The proposed SNN circuit is used for training and recognizing the alphabets/digits in <span><math><mrow><mn>500</mn><mspace></mspace><mi>μ</mi><mi>s</mi></mrow></math></span> using 25 1T-1R RRAM synapses and a single output CMOS LIF neuron.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"205 ","pages":"Article 156145"},"PeriodicalIF":3.2,"publicationDate":"2026-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145617912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Wideband RCS reduction of circularly polarized flexible antenna using polarization conversion metasurface 利用极化转换超表面降低圆极化柔性天线宽带RCS

IF 3.2 3区计算机科学

Aeu-International Journal of Electronics and Communications Pub Date : 2026-02-01 Epub Date: 2026-01-08 DOI: 10.1016/j.aeue.2026.156206

Zheng You, Jinqi Zhang, Xuyin Niu, Guangqian Wu, Shaofeng Wang

{"title":"Wideband RCS reduction of circularly polarized flexible antenna using polarization conversion metasurface","authors":"Zheng You, Jinqi Zhang, Xuyin Niu, Guangqian Wu, Shaofeng Wang","doi":"10.1016/j.aeue.2026.156206","DOIUrl":"10.1016/j.aeue.2026.156206","url":null,"abstract":"<div><div>A flexible wideband circularly polarized (CP) antenna with low radar cross section (RCS) is proposed. It employs a double-layer polarization conversion metasurface (PCM) integrated with a phase control surface (PCS). The metasurface units are orthogonally arranged to form a checkerboard patterned metasurface, which is integrated with a slot antenna array fed by a sequential rotating power divider network with a 90° phase difference. The feed network is fabricated on the flexible printed circuit (FPC). The CP antenna achieves a 3 dB axial ratio (AR) bandwidth from 6.72 GHz to 9.06 GHz and provides over 10 dB radar cross section (RCS) reduction across 5.82 GHz to 19.85 GHz. Under central bending angle from 0° to 90° conditions, the proposed antenna maintains stable RCS reduction and radiation performance, while also suppressing RCS for oblique incident electromagnetic waves within elevation angles from 0° to 45°. The designed metasurface antenna is suitable for radar detection systems and wearable devices.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"206 ","pages":"Article 156206"},"PeriodicalIF":3.2,"publicationDate":"2026-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145927446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A partitioned iterative method for bistatic scattering analysis of PEC cavities with internal–external incident field decomposition 内外入射场分解的PEC腔双稳态散射分析的分割迭代方法

IF 3.2 3区计算机科学

Aeu-International Journal of Electronics and Communications Pub Date : 2026-02-01 Epub Date: 2026-01-08 DOI: 10.1016/j.aeue.2026.156207

Da Huang, Ming Bai

引用次数: 0

Automated design of irregularly shaped microstrip bandpass filters with 2-bit fragment-type structure 2位碎片型结构不规则微带带通滤波器的自动化设计

IF 3.2 3区计算机科学

Aeu-International Journal of Electronics and Communications Pub Date : 2026-02-01 Epub Date: 2026-01-05 DOI: 10.1016/j.aeue.2026.156197

Gongda Hu , Yukun Fang , Dawei Ding

引用次数: 0

Low-power, high-speed ternary adder using multi-threshold GNR transistors for efficient digital computing architectures 采用多阈值GNR晶体管的低功耗、高速三元加法器，用于高效的数字计算架构

IF 3.2 3区计算机科学

Aeu-International Journal of Electronics and Communications Pub Date : 2026-02-01 Epub Date: 2025-11-14 DOI: 10.1016/j.aeue.2025.156139

Kuruva Mahesh, Syed Shameem

{"title":"Low-power, high-speed ternary adder using multi-threshold GNR transistors for efficient digital computing architectures","authors":"Kuruva Mahesh, Syed Shameem","doi":"10.1016/j.aeue.2025.156139","DOIUrl":"10.1016/j.aeue.2025.156139","url":null,"abstract":"<div><div>The demand for efficient adder architectures is rapidly increasing due to the pervasive use of artificial intelligence, cryptography, and other computationally intensive applications. This paper presents a novel low-power, high-speed ternary full adder (TFA) design based on graphene nanoribbon field-effect transistors (GNRFETs). By exploiting the multi-threshold capability of GNRFET devices, the proposed TFA leverages unary operators, transmission gates, and pass-transistor logic to minimize device count while achieving superior performance. The design avoids voltage-degraded paths, thereby guaranteeing full-swing outputs. Robustness is verified through process, voltage, and temperature (PVT) analysis as well as Monte Carlo simulations, confirming stable operation under variability. Comparative evaluation with state-of-the-art GNRFET-based TFAs demonstrates improvements of 6.3 % in delay, 14.6 % in power consumption, and 34.7 % in energy efficiency, along with a 26.1 % reduction in transistor count. All simulations were performed using Synopsys HSPICE with a SPICE-compatible 32-nm GNRFET technology model. Furthermore, when the proposed TFA was applied to the image-processing task as a real-world demonstration, it not only delivered superior image fidelity but also achieved the highest figure of merit (FOM).</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"205 ","pages":"Article 156139"},"PeriodicalIF":3.2,"publicationDate":"2026-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145571867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

OpenCL-accelerated FPGA for real-time AES-128 signal encryption and decryption 用于实时AES-128信号加解密的opencl加速FPGA

IF 3.2 3区计算机科学

Aeu-International Journal of Electronics and Communications Pub Date : 2026-02-01 Epub Date: 2025-12-23 DOI: 10.1016/j.aeue.2025.156187

Iman Firmansyah , Bambang Setiadi , Suyoto Suyoto , Salita Ulitia Prini , Ratna Indrawijaya , Budiman P.A. Rohman , Yoshiki Yamaguchi

{"title":"OpenCL-accelerated FPGA for real-time AES-128 signal encryption and decryption","authors":"Iman Firmansyah , Bambang Setiadi , Suyoto Suyoto , Salita Ulitia Prini , Ratna Indrawijaya , Budiman P.A. Rohman , Yoshiki Yamaguchi","doi":"10.1016/j.aeue.2025.156187","DOIUrl":"10.1016/j.aeue.2025.156187","url":null,"abstract":"<div><div>The growing demand for secure, real-time signal transmission in applications such as IoT, communication systems, and multimedia necessitates low-latency cryptographic solutions. FPGAs are well-suited for this task due to their parallelism and high-throughput capabilities. However, conventional development using hardware description languages (HDLs) can be time-consuming, especially when debugging complex systems. To address these limitations, this work introduces an OpenCL-based framework for implementing real-time AES-128 encryption and decryption on FPGA platforms. The proposed method leverages hardware acceleration and high-level synthesis (HLS) to significantly reduce development time while sustaining high computational performance. A custom analog-to-digital converter (ADC) module based on the Avalon Streaming interface was developed to facilitate continuous data acquisition and real-time signal encryption through OpenCL I/O streaming channels. The system was implemented on an Intel Cyclone V FPGA, interfaced with a dual-channel, 14-bit ADC operating at 100 MHz. Experimental results show that the optimized AES-128 encryption pipeline achieved 98% of its theoretical maximum throughput (3.15 Gbps) when processing streamed ADC input, while the decryption process reached 98% of its peak throughput (9.6 Gbps) when using DDR memory.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"206 ","pages":"Article 156187"},"PeriodicalIF":3.2,"publicationDate":"2026-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145842264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Spatiotemporal modulated multi-functional Non-reciprocal filtering phase shifter with continuously tunable frequency and isolator functionalities 具有连续可调频率和隔离功能的时空调制多功能非互反滤波移相器

IF 3.2 3区计算机科学

Aeu-International Journal of Electronics and Communications Pub Date : 2026-02-01 Epub Date: 2026-01-07 DOI: 10.1016/j.aeue.2025.156192

Girdhari Chaudhary , Yongchae Jeong

{"title":"Spatiotemporal modulated multi-functional Non-reciprocal filtering phase shifter with continuously tunable frequency and isolator functionalities","authors":"Girdhari Chaudhary , Yongchae Jeong","doi":"10.1016/j.aeue.2025.156192","DOIUrl":"10.1016/j.aeue.2025.156192","url":null,"abstract":"<div><div>This paper presents RF co-design approach for a multi-function filtering phase shifter that integrate functionalities of a tunable bandpass filter, continuously tunable phase shifter, and isolator into a single circuit. To support detailed design, the analytical spectral S-parameters of the proposed multi-function non-reciprocal filtering phase shifter have been derived. The isolator functionality (<em>i.e.</em> |S<sub>21</sub>| ≠ |S<sub>12</sub>|) can be achieved using time-varying capacitors modulated by progressive phase shift sinusoidal signal. The frequency and transmission phase can be simultaneously tuned by varying resonant frequency of resonators. For experimental validation, a microstrip line multi-function non-reciprocal filtering phase shifter is designed, fabricated and measured. The measurement demonstrates a phase shift range of 200<sup>o</sup> with forward insertion loss less than 4.9 dB and reverse isolation higher than 30 dB across all phase shift and frequency tuning states. The passband frequency is tuned from 1.42 GHz to 1.75 GHz, providing frequency tunability range of 330 MHz (<em>i.e.</em> tuning ratio: 1:1.2324), while maintaining phase shift range of 200<sup>o</sup> at each frequency tuning state. Furthermore, the measured input and output return losses are higher than 12 dB for each phase shift and passband frequency tuning states.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"206 ","pages":"Article 156192"},"PeriodicalIF":3.2,"publicationDate":"2026-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145977982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A bandwidth controllable dual-band filter integrating effective surface plasmon polaritons and spoof surface plasmon polaritons 一种集成有效表面等离子激元和欺骗表面等离子激元的带宽可控双带滤波器

IF 3.2 3区计算机科学

Aeu-International Journal of Electronics and Communications Pub Date : 2026-02-01 Epub Date: 2025-12-29 DOI: 10.1016/j.aeue.2025.156191

Baoping Ren , Pingping Zhang , Shengli Long , Junhui Qin , Wenlong Zhang , Jun Li , Xuehui Guan

{"title":"A bandwidth controllable dual-band filter integrating effective surface plasmon polaritons and spoof surface plasmon polaritons","authors":"Baoping Ren , Pingping Zhang , Shengli Long , Junhui Qin , Wenlong Zhang , Jun Li , Xuehui Guan","doi":"10.1016/j.aeue.2025.156191","DOIUrl":"10.1016/j.aeue.2025.156191","url":null,"abstract":"<div><div>In this paper, a new dual-band filter based on effective surface plasmon polaritons (ESPPs) and spoof surface plasmon polaritons (SSPPs) is designed. Firstly, a two-layer half-mode substrate integrated waveguide (HMSIW) with half size of SIW is proposed to excite an ESPPs mode, which is used to constitute the lower passband of the dual-band filter. Subsequently, periodic grooves are etched on the top metal layer of the ESPPs waveguide to introduce SSPPs, which facilitates the generation of the upper passband. In contrast to the manner of accomplishing dual-band filtering response by harnessing two ESPPs modes propagating at different interfaces, the design method proposed in this paper allows for simplification of the configuration. Moreover, a high degree of independence is demonstrated in the manipulation of the two passbands. Ultimately, a filter with two passbands centered at 2.18 GHz and 3.43 GHz, and corresponding fractional bandwidth of 13.8% and 37.7% is designed. With the simulated maximum insertion loss of 1.3 dB and return loss better than 10.9 dB within two passbands, the filter possesses good transmission performance. In addition, the rejection level of the stopband between two passbands reaches up to −39 dB, exhibiting favorable isolation. For demonstration, a prototype of the dual-band filter is fabricated and measured. The measured results agree well with the simulations, validating the design method and structure.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"206 ","pages":"Article 156191"},"PeriodicalIF":3.2,"publicationDate":"2026-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145885912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0