A CMOS D-band power combiner with compact size and low insertion loss using packaging-aware design

Abstract

A D-band power combiner is proposed for low-loss interconnection and packaging based on a packaging-aware design methodology, using a 65-nm CMOS technology. The proposed combiner achieves both compact size and low loss by actively incorporating the parasitic effects of RF pads into the circuit design. In particular, the RF pad network, which is indispensable in packaging, is modeled as a combined structure of a transmission line and an effective shunt capacitance, enabling size reduction without performance degradation. The design is based on a careful selection of the characteristic impedance and electrical length of the transmission lines, demonstrating a practical approach for minimizing implementation area while preserving matching performance. In addition, broadband input and output impedance matching is achieved without external matching networks or de-embedding, as the proposed structure inherently compensates for impedance mismatch caused by the RF pads. The proposed power combiner was implemented in a 65-nm CMOS process with 1-poly and 9-metal layers on back-end oxide layers, occupying a compact core area of 0.024 mm², including the RF pads. Measurement results show a minimum insertion loss of 0.7 dB and a 1-dB bandwidth from 103 to 171 GHz, with more than 20 dB isolation between the input ports from 140 to 190 GHz.