Aeu-International Journal of Electronics and Communications最新文献_第7页

Stoch-IMC: A bit-parallel stochastic in-memory computing architecture based on STT-MRAM

IF 3 3区计算机科学

Aeu-International Journal of Electronics and Communications Pub Date : 2025-02-01 DOI: 10.1016/j.aeue.2024.155614

Amir M. Hajisadeghi, Hamid R. Zarandi, Mahmoud Momtazpour

{"title":"Stoch-IMC: A bit-parallel stochastic in-memory computing architecture based on STT-MRAM","authors":"Amir M. Hajisadeghi, Hamid R. Zarandi, Mahmoud Momtazpour","doi":"10.1016/j.aeue.2024.155614","DOIUrl":"10.1016/j.aeue.2024.155614","url":null,"abstract":"<div><div>In-memory computing (IMC) offloads parts of the computations to memory to fulfill the performance and energy demands of applications such as neuromorphic computing, machine learning, and image processing. Fortunately, the main features that stochastic computing (SC) and IMC share, which are low computation complexity and high bit-parallel computation capability, promise great potential for integrating SC and IMC. In this paper, we exploit this potential by using stochastic computation as an approximation method to present effective in-memory computations with a good trade-off among design parameters. To this end, first, commonly used stochastic arithmetic operations of applications are effectively implemented using the primitive logic gates of the IMC method. Next, the in-memory scheduling and mapping of applications are obtained efficiently by a proposed algorithm. This algorithm reduces the computation latency by enabling intra-subarray parallelism while considering the IMC method constraints. Subsequently, a bit-parallel stochastic IMC architecture, Stoch-IMC, is presented that enables bit parallelization of stochastic computations over memory subarrays/banks. To evaluate Stoch-IMC’s effectiveness, various analyses were conducted. Results show average performance improvements of 135.7X and 124.2X across applications compared to binary IMC and related in-memory SC methods, respectively. The results also demonstrate an average energy reduction of 1.5X compared to binary IMC, with limited energy overhead relative to the in-memory SC method. Furthermore, the results reveal average lifetime improvements of 4.9X and 216.3X over binary IMC and in-memory SC methods, respectively, along with high bitflip tolerance.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"190 ","pages":"Article 155614"},"PeriodicalIF":3.0,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143183273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Second-generation voltage conveyor-based first-order all-pass filters and application to quadrature sinusoidal oscillator

IF 3 3区计算机科学

Aeu-International Journal of Electronics and Communications Pub Date : 2025-02-01 DOI: 10.1016/j.aeue.2024.155619

Winai Jaikla , Burin Theppota , Wiset Saksiri , Fabian Khateb , Montree Siripruchyanun

{"title":"Second-generation voltage conveyor-based first-order all-pass filters and application to quadrature sinusoidal oscillator","authors":"Winai Jaikla , Burin Theppota , Wiset Saksiri , Fabian Khateb , Montree Siripruchyanun","doi":"10.1016/j.aeue.2024.155619","DOIUrl":"10.1016/j.aeue.2024.155619","url":null,"abstract":"<div><div>This article describes 2 first-order voltage-mode all-pass filters (APFs) covering leading and lagging phases based on single capacitor and second-generation voltage conveyors (VCIIs). The proposed APFs comprise 2 VCIIs cooperating with 3 resistors and 1 capacitor. The phase angle of the output relative to input signals can be tuned by the single external resistor. Different from previously related works, they use only VCII+ which can be easily realized and less complicated for both integrated circuit architecture and off-the-shelf design. In addition, a 450 mV 1.98 µW VCII based on bulk-driven quasi-floating-gate MOS transistor was developed to be used in this work to achieve ultra low-voltage and low-power consumption. The proposed APFs offer a phase shifting function over a wide range of operating frequency. Its output also provides an accurate sinusoidal signal. The testing results obtained from Cadence Virtuoso System Design Platform simulation are disclosed to investigate different behaviors of the proposed APFs. In addition, the experimental setup using commercially available integrated circuits is shown. From the both results, it is found that they are agreed well with the mentioned anticipations. An application of the proposed APFs in quadrature sinusoidal oscillator is also depicted, it enjoys independent controllability of oscillation condition and oscillation frequency for a wide range of operating frequency with a precise quadrature output signal.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"190 ","pages":"Article 155619"},"PeriodicalIF":3.0,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143183451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Ku-Band dual-sense CP array antenna with polarization converter element

IF 3 3区计算机科学

Aeu-International Journal of Electronics and Communications Pub Date : 2025-02-01 DOI: 10.1016/j.aeue.2024.155637

Mir Hadi Teimouri, Changiz Ghobadi, Javad Nourinia

引用次数: 0

A Compact 2T1C and Cryo-2T1C CMOS Memristor Emulator for Neuromorphic and Quantum Computing

IF 3 3区计算机科学

Aeu-International Journal of Electronics and Communications Pub Date : 2025-02-01 DOI: 10.1016/j.aeue.2025.155683

Sara Paul, Digambar Laxman Bhole, R.K. Kavitha

{"title":"A Compact 2T1C and Cryo-2T1C CMOS Memristor Emulator for Neuromorphic and Quantum Computing","authors":"Sara Paul, Digambar Laxman Bhole, R.K. Kavitha","doi":"10.1016/j.aeue.2025.155683","DOIUrl":"10.1016/j.aeue.2025.155683","url":null,"abstract":"<div><div>In this a new 2T1C (2 Transistors and 1 Capacitor) memristor emulator design which is compact and energy efficient is proposed. It achieves a maximum operating frequency of 150 MHz. The simple circuit design leads to a power consumption of <span><math><mrow><mn>13</mn><mo>.</mo><mn>1</mn><mspace></mspace><mi>μ</mi><mi>W</mi></mrow></math></span> and occupies a minimal area of <span><math><mrow><mn>1</mn><mo>.</mo><mn>25</mn><mspace></mspace><mi>μ</mi><msup><mrow><mi>m</mi></mrow><mrow><mn>2</mn></mrow></msup></mrow></math></span> at room temperature (RT). The chip area and power consumption of 2T1C memristor emulator are 4 and 74 times lesser than the PMME/NMME memristor emulator respectively. In addition to that, a Cryo-2T1C memristor emulator is proposed and its performance is analysed at cryogenic temperature (4.2 K). The Cryo-2T1C could be considered as the first Cryo-CMOS memristor emulator, which has better memristive characteristics at 4.2 K. The Cryo-2T1C memristor has a power consumption of <span><math><mrow><mn>47</mn><mi>μ</mi></mrow></math></span>W and occupies an area of <span><math><mrow><mn>3</mn><mo>.</mo><mn>1</mn><mspace></mspace><mi>μ</mi><msup><mrow><mi>m</mi></mrow><mrow><mn>2</mn></mrow></msup></mrow></math></span> and also operates at a frequency of 150 MHz. To ensure the correctness of memristive characteristics, the proposed designs are verified at various frequencies and voltage levels at RT and 4.2 K in UMC 65 nm process technology. The proposed 2T1C and Cryo-2T1C emulator designs are able to retain the Pinched Hysteresis Loop (PHL) for different process variations and mismatches in both RT and 4.2 K. Hence, the proposed designs are suitable for low power and high frequency applications.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"191 ","pages":"Article 155683"},"PeriodicalIF":3.0,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143285390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An efficient algorithm for modulus operation and its hardware implementation in prime number calculation

IF 3 3区计算机科学

Aeu-International Journal of Electronics and Communications Pub Date : 2025-02-01 DOI: 10.1016/j.aeue.2024.155657

W.A. Susantha Wijesinghe

{"title":"An efficient algorithm for modulus operation and its hardware implementation in prime number calculation","authors":"W.A. Susantha Wijesinghe","doi":"10.1016/j.aeue.2024.155657","DOIUrl":"10.1016/j.aeue.2024.155657","url":null,"abstract":"<div><div>This paper presents a novel algorithm for the modulus operation for FPGA implementation. The proposed algorithm use only addition, subtraction, logical, and bit shift operations, avoiding the complexities and hardware costs associated with multiplication and division. It demonstrates consistent performance across operand sizes ranging from 32-bit to 2048-bit, addressing scalability challenges in cryptographic applications. Implemented in Verilog HDL and tested on a Xilinx Zynq-7000 family FPGA, the algorithm shows a predictable linear scaling of cycle count with bit length difference (BLD), described by the equation <span><math><mrow><mi>y</mi><mo>=</mo><mn>2</mn><mi>x</mi><mo>+</mo><mn>2</mn></mrow></math></span>, where <span><math><mi>y</mi></math></span> represents the cycle count and <span><math><mi>x</mi></math></span> represents the BLD. The application of this algorithm in prime number calculation up to 500,000 shows its practical utility and performance advantages. Comprehensive evaluations reveal efficient resource utilization, robust timing performance, and effective power management, making it suitable for high-performance and resource-constrained platforms. The results indicate that the proposed algorithm significantly improves the efficiency of modular arithmetic operations, with potential implications for cryptographic protocols and secure computing.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"191 ","pages":"Article 155657"},"PeriodicalIF":3.0,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143285375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Substrate integrated waveguide bandpass filter with wide upper stopband

IF 3 3区计算机科学

Aeu-International Journal of Electronics and Communications Pub Date : 2025-02-01 DOI: 10.1016/j.aeue.2025.155663

Ajay Gupta, Arani Ali Khan

{"title":"Substrate integrated waveguide bandpass filter with wide upper stopband","authors":"Ajay Gupta, Arani Ali Khan","doi":"10.1016/j.aeue.2025.155663","DOIUrl":"10.1016/j.aeue.2025.155663","url":null,"abstract":"<div><div>This communication presents the design of a Substrate Integrated Waveguide (SIW) Bandpass Filter (BPF) with wide stopband. The BPF is centered at 3.5 GHz with 0.5 dB equal ripple bandwidth of 4 % and offering a stopband extended up to 40 GHz. The FBW is so chosen that the variation of insertion loss remains within 1 dB over the 3.4 GHz – 3.6 GHz communication band. The proposed vertical integration uses the coupling through rectangular slots on the common plane of two SIW resonators. The slots are positioned to obtain required coupling in the TE<sub>110</sub> mode whereas at other higher order modes, couplings are minimum resulting a wide stopband. In measurement, the BPF offers minimum insertion loss of 2.55 dB at the center frequency of <em>f</em><sub>0</sub> = 3.49 GHz and over 3.42 GHz – 3.59 GHz, it remains better than 3.55 dB. Over the mentioned frequency band, the measured return loss is better than 15 dB. The out of band rejection is at least 50 dB at (<em>f</em><sub>0</sub> + 0.22) GHz and (<em>f</em><sub>0</sub> – 0.2) GHz whereas in the upper stopband, minimum suppression is 40 dB over 3.7 GHz – 20 GHz and remains better than 30 dB up to 40 GHz.</div><div><em>Index Terms</em>— Substrate Integrated Waveguide (SIW), Bandpass filter (BPF), harmonics.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"191 ","pages":"Article 155663"},"PeriodicalIF":3.0,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143285385","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A high accuracy bandgap reference with adaptive mechanical stress compensation

IF 3 3区计算机科学

Aeu-International Journal of Electronics and Communications Pub Date : 2025-02-01 DOI: 10.1016/j.aeue.2025.155674

Pengda Qu , Zhiming Xiao , Yue Zhao , Khalil Yousef

{"title":"A high accuracy bandgap reference with adaptive mechanical stress compensation","authors":"Pengda Qu , Zhiming Xiao , Yue Zhao , Khalil Yousef","doi":"10.1016/j.aeue.2025.155674","DOIUrl":"10.1016/j.aeue.2025.155674","url":null,"abstract":"<div><div>Mechanical stress due to packaging and soldering process is a random non-ideal factor which has been annoying the design of high accuracy analog ICs for a long time. Soldering and mechanical stress would make trimming meaningless after packaging in bandgap reference (BGR) circuits. This paper proposes adaptive stress compensation technique for high accuracy BGR design. This is implemented by feeding the bandgap circuit with a compensation current extracted from the difference of the base-emitter junctions’ voltage (<span><math><msub><mrow><mi>V</mi></mrow><mrow><mi>B</mi><mi>E</mi></mrow></msub></math></span>) variations between NPN and PNP bipolar transistors experiencing the same stress. It was found that the temperature coefficient variations caused by soldering can be enhanced by a factor of 45.3%. The measured temperature coefficient of the reference voltage before soldering is 7.02 ppm/°C, while it is 24.73 ppm/°C after soldering. The proposed compensation technique reduced the measured reference voltage temperature coefficient to 15.03 ppm/°C.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"191 ","pages":"Article 155674"},"PeriodicalIF":3.0,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143285783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Conformal multi-channel MIMO antenna for implantable leadless transcatheter pacing systems

IF 3 3区计算机科学

Aeu-International Journal of Electronics and Communications Pub Date : 2025-02-01 DOI: 10.1016/j.aeue.2024.155621

L. Harlan , M. Susila , Sachin Kumar

{"title":"Conformal multi-channel MIMO antenna for implantable leadless transcatheter pacing systems","authors":"L. Harlan , M. Susila , Sachin Kumar","doi":"10.1016/j.aeue.2024.155621","DOIUrl":"10.1016/j.aeue.2024.155621","url":null,"abstract":"<div><div>This article presents a conformal multi-channel multiple-input-multiple-output (MIMO) antenna designed for a leadless transcatheter pacing system (TPS), operating across the medical implants communications services (MICS) band (401–406 MHz), the wireless medical telemetry services (WMTS) bands (0.608 GHz and 1.4 GHz), and the industrial, scientific and medical (ISM) bands (0.433 GHz, 0.915 GHz, and 2.45 GHz). The proposed antenna has a size of 19 mm × 10 mm × 0.068 mm (0.047<em>λ<sub>g</sub></em> × 0.025<em>λ<sub>g</sub></em> × 0.0001<em>λ<sub>g</sub></em>), and it is constructed on a thin polyimide substrate and wrapped around the TPS capsule’s inner wall, efficiently utilizing the inner space. For the simulation, the proposed antenna and TPS capsule containing dummy electronics are positioned within a homogeneous three-layered phantom (skin-fat-heart) with dielectric properties that mimic the human heart, as well as in a realistic heterogeneous voxel model (Gustav). The antenna is validated for a real environment using an ex-vivo setup comprised of fabricating the antenna prototype and measuring its performance metrics inside pork meat and phantom solution. The proposed MIMO antenna offers good isolation (>25 dB) between antenna elements, and the impedance bandwidths are 710 MHz (0.34 to 1.05 GHz), 560 MHz (1.26 to 1.82 GHz), and 990 MHz (2.01 to 3 GHz). Further, MIMO characteristics are evaluated, and antenna robustness and safety are tested by considering specific absorption rates using human voxel models. The proposed MIMO antenna is the thinnest conformal antenna designed to cover essential biotelemetry frequency bands, including low frequencies of 0.402 GHz and 0.433 GHz with circular polarization, which significantly reduces power consumption and improves transmission range, making it a viable candidate for wireless TPS applications.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"190 ","pages":"Article 155621"},"PeriodicalIF":3.0,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143183300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Conducted interference suppression for Switched-Mode power supplies based on an impedance resonance design of piezoelectric ceramics

IF 3 3区计算机科学

Aeu-International Journal of Electronics and Communications Pub Date : 2025-02-01 DOI: 10.1016/j.aeue.2024.155622

Tao Zhang, Wei Yan, Mengxia Zhou

{"title":"Conducted interference suppression for Switched-Mode power supplies based on an impedance resonance design of piezoelectric ceramics","authors":"Tao Zhang, Wei Yan, Mengxia Zhou","doi":"10.1016/j.aeue.2024.155622","DOIUrl":"10.1016/j.aeue.2024.155622","url":null,"abstract":"<div><div>Suppressing low-frequency conducted interference noise in switched-mode power supplies (SMPS) often presents a challenge. Therefore, this paper proposes a piezoelectric ceramic impedance resonance design method for suppressing conducted interference in SMPS. The advantage of piezoelectric ceramics lies in generation of a lower impedance path near their resonant frequency than capacitors of the same capacitance. In contrast to traditional filtering approaches, the proposed method selectively provides greater attenuation to the peak of conducted interference in SMPS, resulting in increased power density for the SMPS. Additionally, a model correlating the impedance of piezoelectric ceramics to their sizes is established. Based on this model, the sizes of piezoelectric ceramics are designed for the flyback converter. Finally, the interference suppression effect of the designed piezoelectric ceramics is experimentally verified. The experimental results demonstrate the effectiveness of the proposed resonance point design method. In addition, compared to the traditional filter, the method proposed in this paper reduces the weight of the filter by 43.3% and its size by 45.2%.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"190 ","pages":"Article 155622"},"PeriodicalIF":3.0,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143183571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A new CMOS grounded positive capacitance-multiplier and an up-to-date bibliography on capacitance multipliers

IF 3 3区计算机科学

Aeu-International Journal of Electronics and Communications Pub Date : 2025-02-01 DOI: 10.1016/j.aeue.2024.155643

Raj Senani , Abdhesh Kumar Singh , Manish Rai

{"title":"A new CMOS grounded positive capacitance-multiplier and an up-to-date bibliography on capacitance multipliers","authors":"Raj Senani , Abdhesh Kumar Singh , Manish Rai","doi":"10.1016/j.aeue.2024.155643","DOIUrl":"10.1016/j.aeue.2024.155643","url":null,"abstract":"<div><div>The capacitance multiplier circuits using a variety of analog building blocks have currently been receiving prominent attention in the technical literature. This paper presents a classical but unexplored method of synthesising capacitance multiplier and a new grounded positive capacitance multiplier circuit derived by following this approach which employs thirty-two MOSFETs (all operating in saturation) and provides an electronically-controllable capacitance multiplication factor while employing a single grounded capacitor and without using any passive resistors, all of which are desirable features from IC implementation viewpoint. The circuit compares well with the other CMOS-compatible capacitance multipliers known in the earlier literature. The workability of the proposed circuit has been established through SPICE simulations based on 0.18 µm CMOS technology parameters. In the last, in view of the recent surge of interest on capacitance multipliers, an up-to-date bibliography on capacitance multiplier techniques and circuits, covering the period 1966-July 2024, has been provided for the benefit of the readers.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"190 ","pages":"Article 155643"},"PeriodicalIF":3.0,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143183078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0