14-bit Pipelined SAR ADC with PVT-stabilized time-based amplifier

Abstract

This paper presents a 14-bit, 20 MS/s Pipelined successive approximation register (SAR) analog-to-digital converter (ADC), which employs a time-based amplifier (TA) and is suitable for wireless communication systems. The proposed TA employs a combination of a voltage-to-time converter (VTC) and a time-to-voltage converter (TVC), to realize the gain robustness by the ratio of currents and capacitor arrays. The ratio of currents is highly independent of the process-voltage-temperature (PVT) variations because the discharge current in the VTC and the charge current in the TVC stem from the identical bias circuit. As a result, the gain robustness of the proposed TA can improve by up to 91.3% compared to the conventional dynamic amplifier. Benefiting from the proposed TA, the 14-bit Pipelined SAR ADC is designed in a 180 nm CMOS process and a supply voltage of 1.8 V. It can achieve a signal-to-noise and distortion ratio (SNDR) of 78.51 dB and a Walden figure of merit of 31.07 fJ/conversion-step. Under different PVT conditions, the SNDR of the proposed Pipelined SAR ADC varies by less than 1.59 dB.