IEEE Design & Test of Computers最新文献

{"title":"Energy Efficiency Like Your Momma Used to Make","authors":"S. Davidson","doi":"10.1109/MDT.2012.2202529","DOIUrl":"https://doi.org/10.1109/MDT.2012.2202529","url":null,"abstract":"The author muses on having artificially intelligent green buildings that would nag occupants with energy saving tips the way some parents of yesteryear nagged their childeren on the use of electricity in the home.","PeriodicalId":50392,"journal":{"name":"IEEE Design & Test of Computers","volume":"29 1","pages":"61-61"},"PeriodicalIF":0.0,"publicationDate":"2012-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/MDT.2012.2202529","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62469375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Guest Editors' Introduction: Green Buildings","authors":"Yuvraj Agarwal, A. Raghunathan","doi":"10.1109/MDT.2012.2202574","DOIUrl":"https://doi.org/10.1109/MDT.2012.2202574","url":null,"abstract":"h THE GLOBAL DEMAND for energy has been increasing at a rapid pace over the last several decades. The buildings in which we live and work are responsible for a major share of our energy and resource usage. In the United States in 2008, 39% of national energy use, 68% of electricity consumption, and 12% of water consumption was attributed to buildings in a study by the EPA, making buildings the single largest energy sink ahead of transportation and industry. In recent years, the rising costs of using fossil fuels, and the growing awareness of their impact on the environment, have led to concerted efforts to make buildings ‘‘greener.’’ The emerging field of green buildings encompasses various aspects of the building life cycle, including construction, renovation, operation, maintenance and demolition. Naturally, this is a multidisciplinary topic involving diverse fields including civil engineering, chemical engineering, and material science, in addition to electrical engineering and computer science. However, this special issue is motivated by, and focused on, the growing use of technologies that are relevant to the D&T communityVembedded computing, cyberphysical systems, sensor networks, and design principles and methodologies inspired by electronic designVin this area. There is growing consensus that these technologies are key to solving the challenges involved in making buildings greener. From the perspective of the electronics and computing industry, green electronics and computing has two important facetsVreducing the energy consumption in electronic systems themselves, and using them to make physical systems, such as entire buildings, more energy efficient. In other words, we can view electronics and computing as part of the problem (energy consumer), but also as part of the solution (energy efficiency enabler). The articles in this special issue will primarily address the later facet. One of the primary steps in improving energy efficiency of buildings is characterization and measurement, i.e., identifying where the energy is being consumed and where energy can be saved. This is important both at the macroscale, for example, at level of entire enterprises or large campuses, and the microscale by considering individual subsystems within a building. The energy consumed within buildings can be broken down into multiple sourcesVheating and cooling (HVAC), lighting, water management, computing and electronic devices, and other components depending on the building type. A number of efforts have recently looked at breaking down energy use within buildings and university campuses and identifying areas of energy waste which can be improved upon. The natural next step after energy use characterization is to make the energy data within buildings actionableVi.e., attribute the energy consumption of buildings and its subsystems to the actual occupants and activities within the physical spaces. This accurate energy attribution and apportionment serves sev","PeriodicalId":50392,"journal":{"name":"IEEE Design & Test of Computers","volume":"334 1","pages":"5-7"},"PeriodicalIF":0.0,"publicationDate":"2012-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80583554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Defect Oriented Testing for Analog/Mixed-Signal Designs","authors":"B. Kruseman, B. Tasic, C. Hora, J. Dohmen, H. Hashempour, M. V. Beurden, Y. Xing","doi":"10.1109/MDT.2012.2210852","DOIUrl":"https://doi.org/10.1109/MDT.2012.2210852","url":null,"abstract":"In this contribution, the authors describe an application of Defect Oriented Testing (DOT) to commercial mixed-signal designs. A major challenge of DOT application to these designs is the enormous simulation time typically required. The authors address this major challenge with a new algorithm that provides a significant speed-up of over 100x, while at the same time reduces test time by 48% and improves fault coverage by 15%.","PeriodicalId":50392,"journal":{"name":"IEEE Design & Test of Computers","volume":"29 1","pages":"72-80"},"PeriodicalIF":0.0,"publicationDate":"2012-07-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/MDT.2012.2210852","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62470100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Asymmetric Aging and Workload Sensitive Bias Temperature Instability Sensors","authors":"Min Chen, V. Reddy, S. Krishnan, V. Srinivasan, Yu Cao","doi":"10.1109/MDT.2012.2210381","DOIUrl":"https://doi.org/10.1109/MDT.2012.2210381","url":null,"abstract":"Asymmetric aging under different workload profiles requires on-chip aging sensors to be sensitive to signal edge degradation. The authors in this paper present a 45-nm on-chip aging sensor that directly monitors circuit performance degradation during dynamic operation.","PeriodicalId":50392,"journal":{"name":"IEEE Design & Test of Computers","volume":"29 1","pages":"18-26"},"PeriodicalIF":0.0,"publicationDate":"2012-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/MDT.2012.2210381","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62470034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Real-Time Testing Method for Multilevel Signal Interfaces and Its Impact on Test Cost","authors":"M. Ishida, K. Ichiyama, Tasuku Fujibe, D. Watanabe, M. Kawabata","doi":"10.1109/MDT.2012.2210382","DOIUrl":"https://doi.org/10.1109/MDT.2012.2210382","url":null,"abstract":"This paper proposes a real-time testing method for multilevel signal interfaces. It utilizes multilevel drivers that can modulate both the voltage and timing of an output signal, and multilevel comparators based on a dynamic threshold concept. The authors also consider the impact on test cost of the proposed system and compares that cost with a conventional binary test system.","PeriodicalId":50392,"journal":{"name":"IEEE Design & Test of Computers","volume":"29 1","pages":"63-71"},"PeriodicalIF":0.0,"publicationDate":"2012-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/MDT.2012.2210382","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62470049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Improving IC Security Against Trojan Attacks Through Integration of Security Monitors","authors":"S. Narasimhan, W. Yueh, Xinmu Wang, S. Mukhopadhyay, S. Bhunia","doi":"10.1109/MDT.2012.2210183","DOIUrl":"https://doi.org/10.1109/MDT.2012.2210183","url":null,"abstract":"This paper describes using on-chip monitors to significantly improve the sensitivity of side-channel signal analysis techniques to malicious inclusions in integrated circuits known as hardware Trojans.","PeriodicalId":50392,"journal":{"name":"IEEE Design & Test of Computers","volume":"29 1","pages":"37-46"},"PeriodicalIF":0.0,"publicationDate":"2012-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/MDT.2012.2210183","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62469920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Organizational Dynamics: Understanding the Impact of Organizational Structure in Team Productivity","authors":"Michael Jassowski","doi":"10.1109/MDT.2012.2208077","DOIUrl":"https://doi.org/10.1109/MDT.2012.2208077","url":null,"abstract":"While new EDA tools and proven IP cores result in considerable improvement in IC design productivity, but they are not sufficient for today's increasing IC complexity. Understanding the impact of organizational dynamics and investing in advanced program management solutions are necessary, which is exactly the topic that this paper addresses. An earlier version of this paper was presented in the Management Track of DAC.","PeriodicalId":50392,"journal":{"name":"IEEE Design & Test of Computers","volume":"29 1","pages":"52-59"},"PeriodicalIF":0.0,"publicationDate":"2012-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/MDT.2012.2208077","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62469538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Contactless Test of IC Pads, Pins, and TSVs via Standard Boundary Scan","authors":"S. Sunter, A. Roy","doi":"10.1109/MDT.2012.2206363","DOIUrl":"https://doi.org/10.1109/MDT.2012.2206363","url":null,"abstract":"The performance of an IC's inputs and outputs (I/Os) is always specified in IC data sheets and is the performance most likely to be affected by assembly steps. As the speed and number of I/Os increase beyond low-cost ATE capabilities, and I/O pads become smaller (less than 10 microns wide for 3D assemblies), built-in self-test (BIST) of this performance becomes more attractive. This article describes a BIST that exploits relatively low-speed IEEE 1149.1 boundary scan to access the I/Os and test performance with as low as 5 ps calibrated resolution, equivalent to a bandwidth approaching 100 GHz.","PeriodicalId":50392,"journal":{"name":"IEEE Design & Test of Computers","volume":"29 1","pages":"55-62"},"PeriodicalIF":0.0,"publicationDate":"2012-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/MDT.2012.2206363","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62469390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Aging-Aware Power or Frequency Tuning With Predictive Fault Detection","authors":"J. Pachito, C. V. Martins, B. Jacinto, J. Semião, J. C. Vázquez, V. Champac, Marcelino B. Santos, I. Teixeira, João Paulo Teixeira","doi":"10.1109/MDT.2012.2206009","DOIUrl":"https://doi.org/10.1109/MDT.2012.2206009","url":null,"abstract":"This paper presents a methodology to use global and local performance sensors, allowing the circuits to be optimized for power and/or performance.","PeriodicalId":50392,"journal":{"name":"IEEE Design & Test of Computers","volume":"29 1","pages":"27-36"},"PeriodicalIF":0.0,"publicationDate":"2012-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/MDT.2012.2206009","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62469740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design Space Exploration of Parallel Embedded Architectures for Native Clifford Algebra Operations","authors":"S. Franchini, A. Gentile, F. Sorbello, G. Vassallo, S. Vitabile","doi":"10.1109/MDT.2012.2206150","DOIUrl":"https://doi.org/10.1109/MDT.2012.2206150","url":null,"abstract":"Clifford (geometric) algebra is a natural and intuitive way to model geometric objects and their transformations. It has important applications in a variety of fields, including robotics, machine vision and computer graphics, where it has gained a growing interest. This paper presents the design space exploration of parallel embedded architectures that natively support Clifford algebra with different costs, performance and precision. Results show an effective 5x average speedup for Clifford products compared with a software library developed specifically for Clifford algebra.","PeriodicalId":50392,"journal":{"name":"IEEE Design & Test of Computers","volume":"7 1","pages":"60-69"},"PeriodicalIF":0.0,"publicationDate":"2012-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/MDT.2012.2206150","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62469751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}