Contactless Test of IC Pads, Pins, and TSVs via Standard Boundary Scan

Abstract

The performance of an IC's inputs and outputs (I/Os) is always specified in IC data sheets and is the performance most likely to be affected by assembly steps. As the speed and number of I/Os increase beyond low-cost ATE capabilities, and I/O pads become smaller (less than 10 microns wide for 3D assemblies), built-in self-test (BIST) of this performance becomes more attractive. This article describes a BIST that exploits relatively low-speed IEEE 1149.1 boundary scan to access the I/Os and test performance with as low as 5 ps calibrated resolution, equivalent to a bandwidth approaching 100 GHz.