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Heuristic-Based Algorithms for Low-Complexity AV1 Intraprediction 基于启发式的低复杂度AV1内预测算法
IF 2 4区 工程技术
IEEE Design & Test Pub Date : 2023-10-01 DOI: 10.1109/MDAT.2023.3286335
M. Corrêa, D. Palomino, G. Corrêa, L. Agostini
{"title":"Heuristic-Based Algorithms for Low-Complexity AV1 Intraprediction","authors":"M. Corrêa, D. Palomino, G. Corrêa, L. Agostini","doi":"10.1109/MDAT.2023.3286335","DOIUrl":"https://doi.org/10.1109/MDAT.2023.3286335","url":null,"abstract":"This article presents a fast mode decision scheme and a mode-adaptive subsampling algorithm to accelerate AV1 encoding.","PeriodicalId":48917,"journal":{"name":"IEEE Design & Test","volume":"40 1","pages":"26-33"},"PeriodicalIF":2.0,"publicationDate":"2023-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62453903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
SeMAP—A Method to Secure the Communication in NoC-Based Many-Cores SeMAP——一种保证基于NoC的多核通信安全的方法
IF 2 4区 工程技术
IEEE Design & Test Pub Date : 2023-10-01 DOI: 10.1109/MDAT.2023.3277813
R. Faccenda, Gustavo Comarú, L. L. Caimi, F. Moraes
{"title":"SeMAP—A Method to Secure the Communication in NoC-Based Many-Cores","authors":"R. Faccenda, Gustavo Comarú, L. L. Caimi, F. Moraes","doi":"10.1109/MDAT.2023.3277813","DOIUrl":"https://doi.org/10.1109/MDAT.2023.3277813","url":null,"abstract":"This article presents a method for the secure execution of applications on MPSoCs by adopting spatial isolation of applications and a secure communication mechanism with peripherals.","PeriodicalId":48917,"journal":{"name":"IEEE Design & Test","volume":"40 1","pages":"42-51"},"PeriodicalIF":2.0,"publicationDate":"2023-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45724358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Site-to-Site Variation in Analog Multisite Testing: A Survey on Its Detection and Correction 模拟多站点测试中的站点间变化：检测和校正综述
IF 2 4区 工程技术
IEEE Design & Test Pub Date : 2023-10-01 DOI: 10.1109/MDAT.2023.3261799
Praise O. Farayola, Ekaniyere Oko-Odion, Shravan K. Chaganti, Abalhassan Sheikh, S. Ravi, Degang Chen
{"title":"Site-to-Site Variation in Analog Multisite Testing: A Survey on Its Detection and Correction","authors":"Praise O. Farayola, Ekaniyere Oko-Odion, Shravan K. Chaganti, Abalhassan Sheikh, S. Ravi, Degang Chen","doi":"10.1109/MDAT.2023.3261799","DOIUrl":"https://doi.org/10.1109/MDAT.2023.3261799","url":null,"abstract":"Multisite testing, where multiple ICs are tested in parallel sharing the same automatic test equipment, is a widely used method today in IC high-volume test facilities. This article provides a survey of best practices to deal with the problem of site-to-site variation, specifically in the case of analog and mixed-signal ICs.","PeriodicalId":48917,"journal":{"name":"IEEE Design & Test","volume":"40 1","pages":"52-61"},"PeriodicalIF":2.0,"publicationDate":"2023-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46096965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Enabling Security of Heterogeneous Integration: From Supply Chain to In-Field Operations 实现异构集成的安全性:从供应链到现场操作
IF 2 4区 工程技术
IEEE Design & Test Pub Date : 2023-10-01 DOI: 10.1109/MDAT.2023.3270234
Md Sami Ul Islam Sami, H. M. Kamali, Farimah Farahmandi, Fahim Rahman, M. Tehranipoor
{"title":"Enabling Security of Heterogeneous Integration: From Supply Chain to In-Field Operations","authors":"Md Sami Ul Islam Sami, H. M. Kamali, Farimah Farahmandi, Fahim Rahman, M. Tehranipoor","doi":"10.1109/MDAT.2023.3270234","DOIUrl":"https://doi.org/10.1109/MDAT.2023.3270234","url":null,"abstract":"Due to slowdown of Moore’s law and Dennard scaling, modern hardware design has shifted to heterogenous integration (HI) instead of traditional monolithic ICs. However, HI incurs its own security vulnerabilities. In this article, the authors analyze the security issues pertaining to HI and provide defense strategies for the same.","PeriodicalId":48917,"journal":{"name":"IEEE Design & Test","volume":"40 1","pages":"86-95"},"PeriodicalIF":2.0,"publicationDate":"2023-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42717387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
The 41st IEEE VLSI Test Symposium 第41届IEEE VLSI测试研讨会
IF 2 4区 工程技术
IEEE Design & Test Pub Date : 2023-10-01 DOI: 10.1109/mdat.2023.3292798
Naghmeh Karimi
{"title":"The 41st IEEE VLSI Test Symposium","authors":"Naghmeh Karimi","doi":"10.1109/mdat.2023.3292798","DOIUrl":"https://doi.org/10.1109/mdat.2023.3292798","url":null,"abstract":"","PeriodicalId":48917,"journal":{"name":"IEEE Design & Test","volume":"14 1","pages":"113-114"},"PeriodicalIF":2.0,"publicationDate":"2023-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75621257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Reinforcement Learning Framework With Region-Awareness and Shared Path Experience for Efficient Routing in Networks-on-Chip 基于区域感知和共享路径经验的片上网络高效路由强化学习框架
IF 2 4区 工程技术
IEEE Design & Test Pub Date : 2023-08-25 DOI: 10.1109/mdat.2023.3306719
Kamil Khan, Sudeep Pasricha
{"title":"A Reinforcement Learning Framework With Region-Awareness and Shared Path Experience for Efficient Routing in Networks-on-Chip","authors":"Kamil Khan, Sudeep Pasricha","doi":"10.1109/mdat.2023.3306719","DOIUrl":"https://doi.org/10.1109/mdat.2023.3306719","url":null,"abstract":"In this article, the authors introduce a regional congestion-aware reinforcement learning (RL)-based routing policy for Network-on-Chip (NoC) architectures.","PeriodicalId":48917,"journal":{"name":"IEEE Design & Test","volume":"21 1","pages":""},"PeriodicalIF":2.0,"publicationDate":"2023-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138520570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Building an Open-Source DNA Assembler Device 构建一个开源的DNA组装设备
IF 2 4区 工程技术
IEEE Design & Test Pub Date : 2023-08-01 DOI: 10.1109/MDAT.2023.3237942
Boris Oróstica, Isaac Núñez, Tamara Matúte, Felipe Núñez, Fernán Federici
{"title":"Building an Open-Source DNA Assembler Device","authors":"Boris Oróstica, Isaac Núñez, Tamara Matúte, Felipe Núñez, Fernán Federici","doi":"10.1109/MDAT.2023.3237942","DOIUrl":"https://doi.org/10.1109/MDAT.2023.3237942","url":null,"abstract":"This article introduces an open-source thermal cycling machine designed specifically for Golden Gate DNA assembly. The prototype device can achieve efficiency similar to a commercial PCR thermocycler.","PeriodicalId":48917,"journal":{"name":"IEEE Design & Test","volume":"40 1","pages":"69-77"},"PeriodicalIF":2.0,"publicationDate":"2023-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47833580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
IEEE Design & Test Publication Information IEEE Design &测试发布信息
4区 工程技术
IEEE Design & Test Pub Date : 2023-08-01 DOI: 10.1109/mdat.2023.3272163
{"title":"IEEE Design & Test Publication Information","authors":"","doi":"10.1109/mdat.2023.3272163","DOIUrl":"https://doi.org/10.1109/mdat.2023.3272163","url":null,"abstract":"","PeriodicalId":48917,"journal":{"name":"IEEE Design & Test","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135670829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Novel Technique for Manufacturing, System-Level, and In-System Testing of Large SoC Using Functional Protocol-Based High-Speed I/O 基于功能协议的高速I/O在大型SoC制造、系统级和系统内测试中的新技术
IF 2 4区 工程技术
IEEE Design & Test Pub Date : 2023-08-01 DOI: 10.1109/MDAT.2023.3269389
A. Pandey, Brendan Tully, Abhijeet Samudra, Ajay Nagarandal, Karthikeyan Natarajan, Rahul Singhal
{"title":"Novel Technique for Manufacturing, System-Level, and In-System Testing of Large SoC Using Functional Protocol-Based High-Speed I/O","authors":"A. Pandey, Brendan Tully, Abhijeet Samudra, Ajay Nagarandal, Karthikeyan Natarajan, Rahul Singhal","doi":"10.1109/MDAT.2023.3269389","DOIUrl":"https://doi.org/10.1109/MDAT.2023.3269389","url":null,"abstract":"This article discusses the method of using the functional protocol of an existing high-speed I/O port for testing. This method enables reduced GPIO pin requirement during manufacturing test and running full structural content while embedded in a functioning system. Frequency of on-chip scan networks can be increased as it is no longer limited by pin timing bottlenecks of regular, slow-speed I/Os. The same HSAT-based test infrastructure can be used for enabling system-level and in-system test for monitoring throughout the lifecycle of the chip.","PeriodicalId":48917,"journal":{"name":"IEEE Design & Test","volume":"40 1","pages":"17-24"},"PeriodicalIF":2.0,"publicationDate":"2023-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"41883224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Fault-Tolerant Neuromorphic Computing With Memristors Using Functional ATPG for Efficient Recalibration 基于功能ATPG的记忆电阻器容错神经形态计算的高效再校准
IF 2 4区 工程技术
IEEE Design & Test Pub Date : 2023-08-01 DOI: 10.1109/MDAT.2023.3270126
Soyed Tuhin Ahmed, M. Tahoori
{"title":"Fault-Tolerant Neuromorphic Computing With Memristors Using Functional ATPG for Efficient Recalibration","authors":"Soyed Tuhin Ahmed, M. Tahoori","doi":"10.1109/MDAT.2023.3270126","DOIUrl":"https://doi.org/10.1109/MDAT.2023.3270126","url":null,"abstract":"This article focuses on recalibration of neural networks implemented in neuromorphic in-memory computing with memristors. The primary goal of the article is to reduce the amount of data required for recalibration which makes it particularly useful in scenarios where data availability is limited or where recalibration overhead is a concern. Moreover, the proposed approach is robust against both process and temperature variations at a significantly lower overhead compared to related works. This practical method addresses an important issue that can affect the accuracy of neural networks implemented using emerging resistive nonvolatile memories.","PeriodicalId":48917,"journal":{"name":"IEEE Design & Test","volume":"40 1","pages":"42-50"},"PeriodicalIF":2.0,"publicationDate":"2023-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42709978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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