{"title":"Novel Technique for Manufacturing, System-Level, and In-System Testing of Large SoC Using Functional Protocol-Based High-Speed I/O","authors":"A. Pandey, Brendan Tully, Abhijeet Samudra, Ajay Nagarandal, Karthikeyan Natarajan, Rahul Singhal","doi":"10.1109/MDAT.2023.3269389","DOIUrl":null,"url":null,"abstract":"This article discusses the method of using the functional protocol of an existing high-speed I/O port for testing. This method enables reduced GPIO pin requirement during manufacturing test and running full structural content while embedded in a functioning system. Frequency of on-chip scan networks can be increased as it is no longer limited by pin timing bottlenecks of regular, slow-speed I/Os. The same HSAT-based test infrastructure can be used for enabling system-level and in-system test for monitoring throughout the lifecycle of the chip.","PeriodicalId":48917,"journal":{"name":"IEEE Design & Test","volume":null,"pages":null},"PeriodicalIF":1.9000,"publicationDate":"2023-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Design & Test","FirstCategoryId":"5","ListUrlMain":"https://doi.org/10.1109/MDAT.2023.3269389","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0
Abstract
This article discusses the method of using the functional protocol of an existing high-speed I/O port for testing. This method enables reduced GPIO pin requirement during manufacturing test and running full structural content while embedded in a functioning system. Frequency of on-chip scan networks can be increased as it is no longer limited by pin timing bottlenecks of regular, slow-speed I/Os. The same HSAT-based test infrastructure can be used for enabling system-level and in-system test for monitoring throughout the lifecycle of the chip.
期刊介绍:
IEEE Design & Test offers original works describing the models, methods, and tools used to design and test microelectronic systems from devices and circuits to complete systems-on-chip and embedded software. The magazine focuses on current and near-future practice, and includes tutorials, how-to articles, and real-world case studies. The magazine seeks to bring to its readers not only important technology advances but also technology leaders, their perspectives through its columns, interviews, and roundtable discussions. Topics include semiconductor IC design, semiconductor intellectual property blocks, design, verification and test technology, design for manufacturing and yield, embedded software and systems, low-power and energy-efficient design, electronic design automation tools, practical technology, and standards.