{"title":"Strange Loops in Design and Technology: 59th DAC Keynote Speech","authors":"G. De Micheli","doi":"10.1109/MDAT.2023.3284295","DOIUrl":"https://doi.org/10.1109/MDAT.2023.3284295","url":null,"abstract":"This keynote paper highlights the interaction between emerging technologies and software tools to enable the current evolution of electronic design automation systems.","PeriodicalId":48917,"journal":{"name":"IEEE Design & Test","volume":"40 1","pages":"96-103"},"PeriodicalIF":2.0,"publicationDate":"2023-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45149491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Active and Passive Physical Attacks on Neural Network Accelerators","authors":"V. Meyers, Dennis R. E. Gnad, M. Tahoori","doi":"10.1109/MDAT.2023.3253603","DOIUrl":"https://doi.org/10.1109/MDAT.2023.3253603","url":null,"abstract":"This article emphasizes the growing importance of studying defenses for physical attacks on neural network accelerators, and describes approaches based on side-channel attacks and fault-injection attacks.","PeriodicalId":48917,"journal":{"name":"IEEE Design & Test","volume":"40 1","pages":"70-85"},"PeriodicalIF":2.0,"publicationDate":"2023-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43773815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Integrating Machine-Learning Probes in FPGA CAD: Why and How?","authors":"T. Martin, C. Barnes, G. Grewal, S. Areibi","doi":"10.1109/MDAT.2023.3286334","DOIUrl":"https://doi.org/10.1109/MDAT.2023.3286334","url":null,"abstract":"This article discusses challenges posed by current designs and proposes the adoption of machine-learning probes in the FPGA design flow to improve performance.","PeriodicalId":48917,"journal":{"name":"IEEE Design & Test","volume":"40 1","pages":"7-14"},"PeriodicalIF":2.0,"publicationDate":"2023-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62453536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Postpandemic Conferences: The DATE 2023 Experience","authors":"I. O’Connor, R. Wille, A. Pimentel, V. Bertacco","doi":"10.1109/mdat.2023.3287930","DOIUrl":"https://doi.org/10.1109/mdat.2023.3287930","url":null,"abstract":"Digital Object Identier 10.1109/MDAT.2023.3287930 Date of current version: 29 August 2023. DATE is A leading international event providing unique networking opportunities. The conference brings together designers and design automation users, researchers, and vendors, as well as specialists in hardware and software design, testing, and manufacturing of electronic circuits and systems—from system-level hardware and software implementation down to integrated circuit design. Almost four years had passed since we closed the doors on the last in-person edition of the DATE conference. With three online editions due to COVID19 and in anticipation of a return to a full in-person format, the DATE Sponsors Committee felt that the conference needed to put interaction, as well as reinforcing and rebuilding links in the community, at the heart of the event. In this spirit, the postpandemic 2023 edition of DATE had a substantially reworked format intending for significant added value for in-person participation, with more focus on interaction and condensed down to three days. The intent was that, in this way, the community could actually do what DATE is for meeting, discussing, and exchanging the latest progress in design and design automation. The 26th DATE conference was held at the Flanders Meeting and Convention Center in Antwerp, Belgium, from 17 to 19 April 2023 and offered an exciting, wide-ranging technical program.","PeriodicalId":48917,"journal":{"name":"IEEE Design & Test","volume":"34 1","pages":"104-112"},"PeriodicalIF":2.0,"publicationDate":"2023-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88854376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Seyed-Sajad Ahmadpour, Nima Jafari Navimipour, Ali Nawaz Bahar, M. Mosleh, Senay Yalçin
{"title":"An Energy-Aware Nanoscale Design of Reversible Atomic Silicon Based on Miller Algorithm","authors":"Seyed-Sajad Ahmadpour, Nima Jafari Navimipour, Ali Nawaz Bahar, M. Mosleh, Senay Yalçin","doi":"10.1109/MDAT.2023.3261800","DOIUrl":"https://doi.org/10.1109/MDAT.2023.3261800","url":null,"abstract":"Area overhead and energy consumption continue to dominate the scalability issues of modern digital circuits. In this context, atomic silicon and reversible logic have emerged as suitable alternatives to address both issues. In this article, the authors propose novel nano-scale circuit design with low area and energy overheads using the same. In particular, the authors propose a reversible gate with Miller algorithm and atomic silicon technology. This article is extremely relevant in today’s era, when the world is moving toward low area and low energy circuits for use in edge devices.","PeriodicalId":48917,"journal":{"name":"IEEE Design & Test","volume":"40 1","pages":"62-69"},"PeriodicalIF":2.0,"publicationDate":"2023-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43983761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Sandro M. Marques, F. Rossi, M. C. Luizelli, A. C. S. Beck, A. Lorenzon
{"title":"Seamless Thermal Optimization of Parallel Workloads","authors":"Sandro M. Marques, F. Rossi, M. C. Luizelli, A. C. S. Beck, A. Lorenzon","doi":"10.1109/MDAT.2023.3286336","DOIUrl":"https://doi.org/10.1109/MDAT.2023.3286336","url":null,"abstract":"This article proposes a framework for thread-throttling and core-frequency optimization. The framework titled TAURUS is dynamic and transparent to the end user.","PeriodicalId":48917,"journal":{"name":"IEEE Design & Test","volume":" ","pages":"34-41"},"PeriodicalIF":2.0,"publicationDate":"2023-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47894470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}