A Reinforcement Learning Framework With Region-Awareness and Shared Path Experience for Efficient Routing in Networks-on-Chip

IF 1.9 4区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Design & Test Pub Date : 2023-08-25 DOI:10.1109/mdat.2023.3306719

Kamil Khan, Sudeep Pasricha

引用次数: 0

Abstract

In this article, the authors introduce a regional congestion-aware reinforcement learning (RL)-based routing policy for Network-on-Chip (NoC) architectures.

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基于区域感知和共享路径经验的片上网络高效路由强化学习框架

在本文中，作者介绍了一种基于区域拥塞感知强化学习(RL)的片上网络(NoC)架构路由策略。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Design & Test COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-ENGINEERING, ELECTRICAL & ELECTRONIC

CiteScore

3.80

自引率

5.00%

发文量

期刊介绍： IEEE Design & Test offers original works describing the models, methods, and tools used to design and test microelectronic systems from devices and circuits to complete systems-on-chip and embedded software. The magazine focuses on current and near-future practice, and includes tutorials, how-to articles, and real-world case studies. The magazine seeks to bring to its readers not only important technology advances but also technology leaders, their perspectives through its columns, interviews, and roundtable discussions. Topics include semiconductor IC design, semiconductor intellectual property blocks, design, verification and test technology, design for manufacturing and yield, embedded software and systems, low-power and energy-efficient design, electronic design automation tools, practical technology, and standards.