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1978 IEEE 4th Symposium onomputer Arithmetic (ARITH)最新文献

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A feasibility analysis of fixed-slash rational arithmetic 定斜线有理算法的可行性分析
1978 IEEE 4th Symposium onomputer Arithmetic (ARITH) Pub Date : 1978-10-01 DOI: 10.1109/ARITH.1978.6155784
Peter Kornerup, D. Matula
{"title":"A feasibility analysis of fixed-slash rational arithmetic","authors":"Peter Kornerup, D. Matula","doi":"10.1109/ARITH.1978.6155784","DOIUrl":"https://doi.org/10.1109/ARITH.1978.6155784","url":null,"abstract":"An investigation of the feasibility of a finite precision approximate rational arithmetic based on fixed-slash representation of rational numbers is presented. Worst-case and average-case complexity analyses of the involved rounding algorithm (an extended shift-subtract gcd algorithm) are presented. The results are applied to a proposed hardware realization of a fixed-slash arithmetic unit.","PeriodicalId":443215,"journal":{"name":"1978 IEEE 4th Symposium onomputer Arithmetic (ARITH)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1978-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133334633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A comparison of two approaches to multi-operand binary addition 两种多操作数二进制加法方法的比较
1978 IEEE 4th Symposium onomputer Arithmetic (ARITH) Pub Date : 1978-10-01 DOI: 10.1109/ARITH.1978.6155765
D. Atkins, S. Ong
{"title":"A comparison of two approaches to multi-operand binary addition","authors":"D. Atkins, S. Ong","doi":"10.1109/ARITH.1978.6155765","DOIUrl":"https://doi.org/10.1109/ARITH.1978.6155765","url":null,"abstract":"This paper presents the results of one phase of a study concerning methods for addition of P>2 numbers, each encoded as a vector of digits (digit vector) of length N. Such multi-operand addition has been studied most often in the context of reducing a set of partial products to a single result in the implementation of multiplication. More generalized multi-operand addition, most notably in the form of inner product calculations is, however, central to numerous scientific applications of digital computers. Although multi-operand addition is trivially accomplished by accumulation (iteration in time) in any general purpose machine, demands for very high-speed computation, typified by 2- and 3-D signal processing prompt implementation of dedicated, hardware-intensive structures for multi-operand addition. This study, for example, is motivated in part by requirements for rapid simultaneous addition of up to 100, 16-bit operands in the design of a dedicated processor for real-time reconstruction of 3-D images of the beating heart and breathing lungs [1].","PeriodicalId":443215,"journal":{"name":"1978 IEEE 4th Symposium onomputer Arithmetic (ARITH)","volume":"2013 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1978-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133450998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
An interleaved rational/radix arithmetic system for high-precision computations 用于高精度计算的交错有理数/基数算术系统
1978 IEEE 4th Symposium onomputer Arithmetic (ARITH) Pub Date : 1978-10-01 DOI: 10.1109/ARITH.1978.6155781
K. Hwang, T. Chang
{"title":"An interleaved rational/radix arithmetic system for high-precision computations","authors":"K. Hwang, T. Chang","doi":"10.1109/ARITH.1978.6155781","DOIUrl":"https://doi.org/10.1109/ARITH.1978.6155781","url":null,"abstract":"A new interleaved rational/radix number system is proposed for upgrading the precision of normalized Floating-Point (FLP) arithmetic operations without increasing the basic word length. A complete set of rational rounding and arithmetic algorithms are developed. The Average Relative Representation Error (ARRE) of the proposed flexible FLP system is computed through a series of simulation studies on CDC 6500. Our results show a 10% improvement of representation accuracy when compared with the ARRE of conventional FLP system. The architecture of a rational FLP arithmetic processor is also presented. Tradeoffs between operating speed and computing accuracy are discussed.","PeriodicalId":443215,"journal":{"name":"1978 IEEE 4th Symposium onomputer Arithmetic (ARITH)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1978-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122137897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Survey of arithmetic integrated circuits 算术集成电路综述
1978 IEEE 4th Symposium onomputer Arithmetic (ARITH) Pub Date : 1978-10-01 DOI: 10.1109/ARITH.1978.6155760
S. Waser
{"title":"Survey of arithmetic integrated circuits","authors":"S. Waser","doi":"10.1109/ARITH.1978.6155760","DOIUrl":"https://doi.org/10.1109/ARITH.1978.6155760","url":null,"abstract":"The purpose of this report is to provide the state-of-the-art of high performance arithmetic integrated circuits (ICs). The survey concentrates on arithmetic ICs that are designed to improve execution speed over software techniques, therefore, no calculator chips are surveyed. In order to understand the difficulties encountered in fabricating high speed arithmetic ICs, we start the article with a discussion on semiconductor technology. Next, we survey the various arithmetic elements that are available in monolithic form: ALUs, Data Slices, Multipliers, Floating Point Processors, and ROMs. Finally, we conclude with a comment on digital signal processing and a discussion of the future trends in arithmetic ICs.","PeriodicalId":443215,"journal":{"name":"1978 IEEE 4th Symposium onomputer Arithmetic (ARITH)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1978-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129809598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Application of the residue number system to computer processing of digital signals 余数系统在数字信号计算机处理中的应用
1978 IEEE 4th Symposium onomputer Arithmetic (ARITH) Pub Date : 1978-10-01 DOI: 10.1109/ARITH.1978.6155782
G. Jullien, W. Miller
{"title":"Application of the residue number system to computer processing of digital signals","authors":"G. Jullien, W. Miller","doi":"10.1109/ARITH.1978.6155782","DOIUrl":"https://doi.org/10.1109/ARITH.1978.6155782","url":null,"abstract":"The residue number system offers parallel processing, digital hardware, implementations for the binary operations of addition, subtraction and multiplication. This paper discusses the use of the residue number system in implementing digital signal processing functions, in which these binary operations abound. The paper covers implementations using arrays of read only memories, and briefly discusses the use of parallel microprocessor structures. ROM array implementations of scaling operations are also presented.","PeriodicalId":443215,"journal":{"name":"1978 IEEE 4th Symposium onomputer Arithmetic (ARITH)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1978-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127896376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A modified bi-imaginary number system 一个改进的双虚数系统
1978 IEEE 4th Symposium onomputer Arithmetic (ARITH) Pub Date : 1978-10-01 DOI: 10.1109/ARITH.1978.6155756
A. G. Slekys, A. Avizienis
{"title":"A modified bi-imaginary number system","authors":"A. G. Slekys, A. Avizienis","doi":"10.1109/ARITH.1978.6155756","DOIUrl":"https://doi.org/10.1109/ARITH.1978.6155756","url":null,"abstract":"In this paper the properties of p-imaginary number systems are reviewed and a modified bi-imaginary number system is introduced as a special case with p = 2. Major properties, including conversion of integer and floating point operands represented in a radix +p system, range, sign and zero tests, and shifting are discussed. The ability to represent the operands as vectors of radix −2 digits suggests advantages in implementing machine-usable arithmetic algorithms.","PeriodicalId":443215,"journal":{"name":"1978 IEEE 4th Symposium onomputer Arithmetic (ARITH)","volume":"207 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1978-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122975506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A feasibility analysis of binary fixed-slash and floating-slash number systems 二进制定斜线和浮点斜线数系统的可行性分析
1978 IEEE 4th Symposium onomputer Arithmetic (ARITH) Pub Date : 1978-10-01 DOI: 10.1109/ARITH.1978.6155752
D. Matula, Peter Kornerup
{"title":"A feasibility analysis of binary fixed-slash and floating-slash number systems","authors":"D. Matula, Peter Kornerup","doi":"10.1109/ARITH.1978.6155752","DOIUrl":"https://doi.org/10.1109/ARITH.1978.6155752","url":null,"abstract":"Design and analysis of finite precision rational number systems based on fixed-slash and floating-slash representation is pursued. Natural formats for binary fixed-slash and binary floating-slash number representation in computer words are described. Compatibility with standard integer representation is obtained. Redundancy in the' representation is shown to be minimal. Arithmetic register requirements are considered. Worst case and average case rounding errors are determined, and the concept of adaptive variable precision in the rounding is developed.","PeriodicalId":443215,"journal":{"name":"1978 IEEE 4th Symposium onomputer Arithmetic (ARITH)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1978-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131559752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
On arithmetic inter-relationships and hardware interchangeabiltty of negabinary and binary systems 论负二进制和二进制的算术相互关系和硬件互换性
1978 IEEE 4th Symposium onomputer Arithmetic (ARITH) Pub Date : 1978-10-01 DOI: 10.1109/ARITH.1978.6155763
D. Agrawal
{"title":"On arithmetic inter-relationships and hardware interchangeabiltty of negabinary and binary systems","authors":"D. Agrawal","doi":"10.1109/ARITH.1978.6155763","DOIUrl":"https://doi.org/10.1109/ARITH.1978.6155763","url":null,"abstract":"Recent use of the negabinary system in the application oriented digital hardware, has encouraged the search for suitable arithmetic algorithms in −2 base. These algorithms have been directly utilized in designing logic circuits and several logic implementations have been reported in the literature. The main objective of this paper is to show the close relationship between +2 base addition and −2 base negative addition. Two possible ways of utilizing binary adders for performing negabinary addition and their underlying theories are presented. Two similar techniques of using negabinary adders for binary addition are also considered in detail. An interesting aspect of this investigation about negabinary base is that negative addition (rather than just addition) seems to be the primitive operation from logic complexity and interchangeability of +2 and −2 adders point of view. The technique of adding two numbers in one system by the adders of the other system is extended here for multiple operand addition. This requires inclusion of an additional correction factor. Further, the additive algorithms of this work lead to four simple conversion processes of number from one system to another. This paper seems to be a realistic step towards the use of similar hardware for +2 and −2 bases and hence this allows an instantaneous flexibility on the selection of number system. It is believed that this paper will attract more attention on the use of −2 base system for the design of special purpose digital machines and process controllers.","PeriodicalId":443215,"journal":{"name":"1978 IEEE 4th Symposium onomputer Arithmetic (ARITH)","volume":"147 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1978-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121477818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Exact arithmetic using a variable-length P-ADIC representation 使用可变长度P-ADIC表示的精确算术
1978 IEEE 4th Symposium onomputer Arithmetic (ARITH) Pub Date : 1978-10-01 DOI: 10.1109/ARITH.1978.6155779
R. Horspool, E. Hehner
{"title":"Exact arithmetic using a variable-length P-ADIC representation","authors":"R. Horspool, E. Hehner","doi":"10.1109/ARITH.1978.6155779","DOIUrl":"https://doi.org/10.1109/ARITH.1978.6155779","url":null,"abstract":"The p-adic number system is introduced and developed into a form suitable for performing exact arithmetic in computers. The proposed representation has several desirable attributes: the four standard arithmetic operations have a simple consistent form, the programmer has the ability to choose the precise degree of accuracy in his calculations and the variable-length nature of the representation achieves compact encodings.","PeriodicalId":443215,"journal":{"name":"1978 IEEE 4th Symposium onomputer Arithmetic (ARITH)","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1978-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129997473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
High-speed multiplication and multiple summand addition 高速乘法和多次求和加法
1978 IEEE 4th Symposium onomputer Arithmetic (ARITH) Pub Date : 1978-10-01 DOI: 10.1109/ARITH.1978.6155788
R. S. Lim
{"title":"High-speed multiplication and multiple summand addition","authors":"R. S. Lim","doi":"10.1109/ARITH.1978.6155788","DOIUrl":"https://doi.org/10.1109/ARITH.1978.6155788","url":null,"abstract":"The problem of high-speed multiplication is considered from the viewpoint of summand generation and summand summation. The goal is to obtain at least a 2's-complement, 32-bit floating-point (sign plus 24-bit fraction) multiplication in 10 to 20 ns using ECL LSI packages. Summand generation is implemented by mxm-bit multipliers. The optimum values for m are 9, 13, 17, or 21. Summand summation is implemented by a row of (p, 2) column-summing counters. The (3, 2), (5, 2), and (7, 2) counters are optimum choices. These counters compress p inputs into two outputs plus nonpropagating carry bits, where these bits are added to the next higher-order stage with at most two full adder delays.","PeriodicalId":443215,"journal":{"name":"1978 IEEE 4th Symposium onomputer Arithmetic (ARITH)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1978-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116930734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
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