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1978 IEEE 4th Symposium onomputer Arithmetic (ARITH)最新文献

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An on-line square rooting algorithm 一种在线平方根算法
1978 IEEE 4th Symposium onomputer Arithmetic (ARITH) Pub Date : 1978-10-01 DOI: 10.1109/ARITH.1978.6155773
M. Ercegovac
{"title":"An on-line square rooting algorithm","authors":"M. Ercegovac","doi":"10.1109/ARITH.1978.6155773","DOIUrl":"https://doi.org/10.1109/ARITH.1978.6155773","url":null,"abstract":"An on-line algorithm for computing square roots in a radix 2, normalized floating-point number system with the redundant digit set {-1, 0, 1} is described. The algorithm has on-line delay of one and it is amenable for modular implementation. A systematic approach, used in deriving this algorithm, is presented in detail.","PeriodicalId":443215,"journal":{"name":"1978 IEEE 4th Symposium onomputer Arithmetic (ARITH)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1978-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114587254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 35
Some experiments using interval arithmetic 区间算法的一些实验
1978 IEEE 4th Symposium onomputer Arithmetic (ARITH) Pub Date : 1978-10-01 DOI: 10.1109/ARITH.1978.6155754
Eric K. Reuter, John P. Jeter, J. W. Anderson, B. Shriver
{"title":"Some experiments using interval arithmetic","authors":"Eric K. Reuter, John P. Jeter, J. W. Anderson, B. Shriver","doi":"10.1109/ARITH.1978.6155754","DOIUrl":"https://doi.org/10.1109/ARITH.1978.6155754","url":null,"abstract":"This paper reviews past experiences and discusses future work in the area of interval arithmetic at the University of Southwestern Louisiana(USL). Two versions of interval arithmetic were developed and implemented at USL(∗). An interval data type declaration and the necessary mathematical functions for this data type were added to Fortran via the preprocessor Augment(4, 5). In the first version, the endpoints of the intervals were represented as single percision floating point numbers. In the other version, the endpoints were represented to 56 decimal digits. Production engineering programs were run as benchmarks(8). The accumulation ot computational and algorithmic error could be observed as a widening of the intervals. The benchmarks were also run in normal single and double precision arithmetic. In some instances, the result obtained from a single or double precision calculation was not bounded by the corresponding interval result indicating some problem with the algorithm. The widening of an interval does not necessarily indicate a data sensitivity nor error in an algorithm. However, these large intervals can be used as indicator of no problems. As could be expected, the 56-decimal digit precision interval gave better results in terms of smaller intervals due to the increased amount of precision. The obvious problem with this version is that the amount of overhead required for its execution is high.","PeriodicalId":443215,"journal":{"name":"1978 IEEE 4th Symposium onomputer Arithmetic (ARITH)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1978-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125490462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Design of arithmetic elements for Burroughs Scientific Processor Burroughs科学处理机的算术元件设计
1978 IEEE 4th Symposium onomputer Arithmetic (ARITH) Pub Date : 1978-10-01 DOI: 10.1109/ARITH.1978.6155777
D. Gajski, Louis P. Rubinfield
{"title":"Design of arithmetic elements for Burroughs Scientific Processor","authors":"D. Gajski, Louis P. Rubinfield","doi":"10.1109/ARITH.1978.6155777","DOIUrl":"https://doi.org/10.1109/ARITH.1978.6155777","url":null,"abstract":"The design criteria and implementation of the Arithmetic Element (AE) of the Burroughs Scientific Processor, a vector machine intended for scientific computation requiring speed of up to 50 million floating-point operations per second, is discussed. An array of 16 AEs operate in lockstep mode, executing the same instruction on 16 sets of data. The 16 AEs are one stage in a pipeline which consists of 17 memory modules, an input alignment network, and an output alignment network. The AE itself is not pipelined. It can perform over one hundred different operations including a floating-point addition, subtraction and multiplication, division, square root, among the others. Eight registers are provided for the storage of intermediate values and results. Modulo 3 residue arithmetic is used for checking hardware failures.","PeriodicalId":443215,"journal":{"name":"1978 IEEE 4th Symposium onomputer Arithmetic (ARITH)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1978-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126801028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A unified approach to a class of number systems 一类数字系统的统一方法
1978 IEEE 4th Symposium onomputer Arithmetic (ARITH) Pub Date : 1978-10-01 DOI: 10.1109/ARITH.1978.6155783
I. Koren, Yoram Maliniak
{"title":"A unified approach to a class of number systems","authors":"I. Koren, Yoram Maliniak","doi":"10.1109/ARITH.1978.6155783","DOIUrl":"https://doi.org/10.1109/ARITH.1978.6155783","url":null,"abstract":"A unified approach to a broad class of number systems is proposed in this paper. This class contains all positive and negative radix systems and other well-known number systems. The proposed approach enables us to develop a single set of algorithms for arithmetic operations and conversion methods between number systems.","PeriodicalId":443215,"journal":{"name":"1978 IEEE 4th Symposium onomputer Arithmetic (ARITH)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1978-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116537076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Merged arithmetic for signal processing 信号处理的合并算法
1978 IEEE 4th Symposium onomputer Arithmetic (ARITH) Pub Date : 1978-10-01 DOI: 10.1109/ARITH.1978.6155758
E. Swartzlander
{"title":"Merged arithmetic for signal processing","authors":"E. Swartzlander","doi":"10.1109/ARITH.1978.6155758","DOIUrl":"https://doi.org/10.1109/ARITH.1978.6155758","url":null,"abstract":"The concept of merged arithmetic is introduced and applied to signal processing. The basic idea involves synthesizing a composite arithmetic function (e.g., a complex multiply) directly instead of decomposing it into multiply and add operations as is conventional practice. This approach results in a simpler design which is also faster.","PeriodicalId":443215,"journal":{"name":"1978 IEEE 4th Symposium onomputer Arithmetic (ARITH)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1978-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114554692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
Two methods for fast integer binary-BCD conversion 两种快速整数二进制- bcd转换方法
1978 IEEE 4th Symposium onomputer Arithmetic (ARITH) Pub Date : 1978-10-01 DOI: 10.1109/ARITH.1978.6155755
F. Schreiber, R. Stefanelli
{"title":"Two methods for fast integer binary-BCD conversion","authors":"F. Schreiber, R. Stefanelli","doi":"10.1109/ARITH.1978.6155755","DOIUrl":"https://doi.org/10.1109/ARITH.1978.6155755","url":null,"abstract":"Two methods for performing binary-BCD conversion of positive integers are discussed. The principle which underlies both methods in the repeated division by five and then by two, obtained the first by means of substructions performed from left to right, the second by shifting bits before next subtraction. It is shown that these methods work in a time which is linear with the length in bit of the number to be converted. A ROM solution is proposed and its complexity is compared with that of other methods.","PeriodicalId":443215,"journal":{"name":"1978 IEEE 4th Symposium onomputer Arithmetic (ARITH)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1978-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132721705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Computational design alternatives with microprocessor-based systems 基于微处理器系统的计算设计替代方案
1978 IEEE 4th Symposium onomputer Arithmetic (ARITH) Pub Date : 1978-10-01 DOI: 10.1109/ARITH.1978.6155787
S. Lillevik, P. D. Fisher
{"title":"Computational design alternatives with microprocessor-based systems","authors":"S. Lillevik, P. D. Fisher","doi":"10.1109/ARITH.1978.6155787","DOIUrl":"https://doi.org/10.1109/ARITH.1978.6155787","url":null,"abstract":"This paper examines and characterizes four elemental hardware computational design alternatives (CDA's) and presents a structured approach to computational section design which incorporates a rigorous, theoretic foundation. The DIRECT CDA incorporates a single microprocessor (μP) and memory. The AU CDA contains a μP, memory, and arithmetic unit. A μP, memory, and calculator chip comprise the CALC CDA. Finally, several μP's and memories in a Master/Slave arrangement implement the multiple-μP mμP CDA. A common set of attributes — precision, speed and cost — facilitates comparison. Using these attributes, Multiattribute Utility Theory assesses a numeric quantity, the utility, to represent each CDA's relative usefulness. Thus, design involves selecting the CDA with the greatest utility.","PeriodicalId":443215,"journal":{"name":"1978 IEEE 4th Symposium onomputer Arithmetic (ARITH)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1978-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124782276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Parallel adders using standard plas 使用标准plas的并行加法器
1978 IEEE 4th Symposium onomputer Arithmetic (ARITH) Pub Date : 1978-10-01 DOI: 10.1109/ARITH.1978.6155761
A. Weinberger
{"title":"Parallel adders using standard plas","authors":"A. Weinberger","doi":"10.1109/ARITH.1978.6155761","DOIUrl":"https://doi.org/10.1109/ARITH.1978.6155761","url":null,"abstract":"PLA adders are described that add in one cycle and require a reasonable number of product terms for an 8, 16, or even a 32-bit adder. A procedure is also described for minimizing the number of product terms for any size adder.","PeriodicalId":443215,"journal":{"name":"1978 IEEE 4th Symposium onomputer Arithmetic (ARITH)","volume":"295 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1978-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125520066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Convergence guarantee and improvements for a fast hardware exponential and logarithm evaluation scheme 一种快速硬件指数和对数评估方案的收敛保证与改进
1978 IEEE 4th Symposium onomputer Arithmetic (ARITH) Pub Date : 1978-10-01 DOI: 10.1109/ARITH.1978.6155762
C. Wrathall, T. C. Chen
{"title":"Convergence guarantee and improvements for a fast hardware exponential and logarithm evaluation scheme","authors":"C. Wrathall, T. C. Chen","doi":"10.1109/ARITH.1978.6155762","DOIUrl":"https://doi.org/10.1109/ARITH.1978.6155762","url":null,"abstract":"In one iteration, Chen's algorithm for evaluating exponentials and logarithms advances by 2 bits on the average, yet may not advance at all. Analysis reveals that the no-advance situation actually paves the way for sizable advance in the next iteration, and the guaranteed advance, after a one iteration overhead, is one bit per iteration. Two new schemes raise the guaranteed advance to 1.5 bits per iteration, after a two-iteration overhead, while maintaining the original requirement of one stored constant per operand bit. Adopting as a figure of merit the following quantity Q = advance per iteration/memory words per operand bit for the steady-state iterations, the new schemes appears to be better than other methods heretofore proposed.","PeriodicalId":443215,"journal":{"name":"1978 IEEE 4th Symposium onomputer Arithmetic (ARITH)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1978-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115624723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Multivariable polynomial processing — Applications to interpolation 多变量多项式处理。在插值中的应用
1978 IEEE 4th Symposium onomputer Arithmetic (ARITH) Pub Date : 1978-10-01 DOI: 10.1109/ARITH.1978.6155785
E. V. Kriphnamurthy, H. Venkateswaran
{"title":"Multivariable polynomial processing — Applications to interpolation","authors":"E. V. Kriphnamurthy, H. Venkateswaran","doi":"10.1109/ARITH.1978.6155785","DOIUrl":"https://doi.org/10.1109/ARITH.1978.6155785","url":null,"abstract":"A data-structure suitable for multivariable polynomial processing is introduced. Using this data-structure, arithmetic algorithms are described for addition, subtraction and multiplication of multivariable polynomials; also algorithms are described for forming the inner product and tensor product of vectors, whose components are multivariable polynomials. Application of these algorithms. for multivariable cardinal spline approximation is described in detail.","PeriodicalId":443215,"journal":{"name":"1978 IEEE 4th Symposium onomputer Arithmetic (ARITH)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1978-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114325226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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