使用标准plas的并行加法器

1978 IEEE 4th Symposium onomputer Arithmetic (ARITH) Pub Date : 1978-10-01 DOI:10.1109/ARITH.1978.6155761

A. Weinberger

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引用次数: 1

摘要

PLA加法器被描述为在一个周期内添加，并且对于8位、16位甚至32位加法器需要合理数量的乘积项。还描述了最小化任何尺寸加法器的乘积项数的过程。

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Parallel adders using standard plas

PLA adders are described that add in one cycle and require a reasonable number of product terms for an 8, 16, or even a 32-bit adder. A procedure is also described for minimizing the number of product terms for any size adder.

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来源期刊

1978 IEEE 4th Symposium onomputer Arithmetic (ARITH)

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