2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)最新文献_第4页

Logic synthesis for manufacturability considering regularity and lithography printability 考虑规则性和平版印刷性的可制造性逻辑综合

2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2013-08-01 DOI: 10.1109/ISVLSI.2013.6654638

Lucas Machado, V. D. Bem, F. Moll, Sergio Gómez, R. Ribas, A. Reis

引用次数: 2

Breaking power delivery walls using voltage stacking 利用电压叠加打破电力输送墙

2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2013-08-01 DOI: 10.1109/ISVLSI.2013.6654642

M. Stan

引用次数: 0

On analyzing and mitigating SRAM BER due to random thermal noise 随机热噪声对SRAM误码率的影响

2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2013-08-01 DOI: 10.1109/ISVLSI.2013.6654652

Vikram B. Suresh, S. Kundu

{"title":"On analyzing and mitigating SRAM BER due to random thermal noise","authors":"Vikram B. Suresh, S. Kundu","doi":"10.1109/ISVLSI.2013.6654652","DOIUrl":"https://doi.org/10.1109/ISVLSI.2013.6654652","url":null,"abstract":"Embedded memory is a major design element in microprocessors and system-on-chips. Typically embedded memories are constituted of SRAM circuits. SRAM cell stability is a major determinant of Vmin for ultra-low power mobile computing. At low voltages, thermal noise plays a role in SRAM cell stability. In this work, we present an analysis of random thermal noise on stability of SRAM bit cells. Of specific concern to us, is the process of device aging, where a transistor performance may degrade over time. A marginal SRAM bit cell that is stable at the time of manufacturing test may become susceptible to random bit flips due to thermal noise under aging related degradation. In order to quantify the impact of random thermal noise on SRAM cell stability, we present a methodology to measure the expected Random Bit Error Rate (BER). Such analysis helps select minimum supply voltage to meet target BER. Next we propose selective multi-level WL control for access transistors of marginal cells to improve their stability during read and write operations. Simulation studies show a BER of ~1 per 106 reads at a low operating voltage of 700mV. The proposed design techniques reduce probability of random bit errors to nearly zero at marginal performance penalty. Application of stochastic analysis to a sample 2MB cache shows >10X improvement in BER and hence improved longevity of marginal cells.","PeriodicalId":439122,"journal":{"name":"2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132725338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Design & implementation of software defined radios on a homogeneous multi-processor architecture 软件定义无线电在同构多处理器架构上的设计与实现

2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2013-08-01 DOI: 10.1109/ISVLSI.2013.6654646

Roberto Airoldi, J. Nurmi

引用次数: 0

Behavioral model of integrated qubit gates for quantum reversible logic design 量子可逆逻辑设计中集成量子比特门的行为模型

2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2013-08-01 DOI: 10.1109/ISVLSI.2013.6654658

Matthew Lewandowski, N. Ranganathan, Matthew Morrison

引用次数: 12

A novel optimization method for reversible logic circuit minimization 一种新的可逆逻辑电路最小化优化方法

2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2013-08-01 DOI: 10.1109/ISVLSI.2013.6654656

Matthew Morrison, N. Ranganathan

引用次数: 15

A double-width algorithmic balancing to prevent power analysis Side Channel Attacks in AES 一种防止AES中功率分析侧信道攻击的双宽度算法平衡

2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2013-08-01 DOI: 10.1109/ISVLSI.2013.6654626

Ankita Arora, Jude Angelo Ambrose, Jorgen Peddersen, S. Parameswaran

{"title":"A double-width algorithmic balancing to prevent power analysis Side Channel Attacks in AES","authors":"Ankita Arora, Jude Angelo Ambrose, Jorgen Peddersen, S. Parameswaran","doi":"10.1109/ISVLSI.2013.6654626","DOIUrl":"https://doi.org/10.1109/ISVLSI.2013.6654626","url":null,"abstract":"Advanced Encryption Standard (AES) is one of the most widely used cryptographic algorithms in embedded systems, and is deployed in smart cards, mobile phones and wireless applications. Researchers have found various techniques to attack the encrypted data or the secret key using Side Channel information (execution time, power variations, electro migration, sound, etc.). Power analysis attack is most prevalent out of all Side Channel Attacks (SCAs), the popular being the Differential Power Analysis (DPA). Balancing of signal transitions is one of the methods by which a countermeasure is implemented. Existing balancing solutions to counter power analysis attacks are either costly in terms of power and area or involve much complexity, hence lacks practicality. This paper for the first time proposes a double-width single core (earlier methods used two separate cores)processor algorithmic balancing to obfuscate power variations resulting in a DPA resistant system. The countermeasure only includes code/algorithmic modifications, hence can be easily deployed in any embedded system with a 16 bits bitwidth (or wider) processor. A DPA attack is demonstrated on the Double Width Single Core (DWSC) solution. The attack proved unsuccessful in finding the correct secret key. The instruction memory size overhead is only 16.6% while data memory increases by 15.8%.","PeriodicalId":439122,"journal":{"name":"2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"318 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122839348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

Dynamic encryption key design and management for memory data encryption in embedded systems 嵌入式系统内存数据加密的动态加密密钥设计与管理

2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2013-08-01 DOI: 10.1109/ISVLSI.2013.6654625

Mei Hong, Hui Guo, S. Parameswaran

{"title":"Dynamic encryption key design and management for memory data encryption in embedded systems","authors":"Mei Hong, Hui Guo, S. Parameswaran","doi":"10.1109/ISVLSI.2013.6654625","DOIUrl":"https://doi.org/10.1109/ISVLSI.2013.6654625","url":null,"abstract":"To effectively encrypt data memory contents of an embedded processor, multiple keys which are dynamically changed are necessary. However, the resources required to store and manage these keys on-chip (so that they are secure) can be extensive. This paper presents a design where each dynamic key is determined by a random number, a counter value, and a memory address, and is unique to the data in a memory location. The counter value, dedicated to a given memory location, controls the duration of the random number for the key associated with the location. The counter table and random number table are used for key storage. We reduce on-chip resources by customizing the counter table and allowing a pool of random numbers to be shared amongst the keys. The random numbers are dynamically updated during the application execution. We propose a key generation and management scheme such that the random number pool is extremely small (hence low memory consumption) yet sufficient for the uniqueness and randomness of each dynamic key. Experiments on a set of applications show that on average, large overhead (90% on chip area and 92% on power consumption) can be saved for a same security level, when compared to the state-of-the-art approach.","PeriodicalId":439122,"journal":{"name":"2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121218509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

A yield-driven regular layout synthesis 产量驱动的规则布局综合

2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2013-08-01 DOI: 10.1109/ISVLSI.2013.6654649

C. Meinhardt, R. Reis

引用次数: 2

Memory subsystem architecture design for multimedia applications 多媒体应用的存储器子系统体系结构设计

2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2013-08-01 DOI: 10.1109/ISVLSI.2013.6654645

A. Bonatto, A. Susin

引用次数: 5