2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)最新文献

On-chip clock error characterization for clock distribution system 时钟分配系统的片上时钟误差表征

2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2013-11-07 DOI: 10.1109/ISVLSI.2013.6654630

Chuan Shan, D. Galayko, F. Anceau

引用次数: 2

A novel tool flow for increased routing configuration similarity in multi-mode circuits 一种在多模电路中增加路由配置相似性的新型工具流

2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2013-11-07 DOI: 10.1109/ISVLSI.2013.6654629

Brahim Al Farisi, Elias Vansteenkiste, Karel Bruneel, D. Stroobandt

{"title":"A novel tool flow for increased routing configuration similarity in multi-mode circuits","authors":"Brahim Al Farisi, Elias Vansteenkiste, Karel Bruneel, D. Stroobandt","doi":"10.1109/ISVLSI.2013.6654629","DOIUrl":"https://doi.org/10.1109/ISVLSI.2013.6654629","url":null,"abstract":"A multi-mode circuit implements the functionality of a limited number of circuits, called modes, of which at any given time only one needs to be realised. Using run-time reconfiguration (RTR) of an FPGA, all the modes can be time-multiplexed on the same reconfigurable region, requiring only an area that can contain the biggest mode. Typically, conventional run-time reconfiguration techniques generate a configuration of the reconfigurable region for every mode separately. This results in configurations that are bit-wise very different. Thus, in this case, many bits need to be changed in the configuration memory to switch between modes, leading to long reconfiguration times. In this paper we present a novel tool flow that retains the placement of the conventional RTR flow, but uses TRoute, a reconfiguration-aware connection router, to implement the connections of all modes simultaneously. DRoute stimulates the sharing of routing resources between connections of different modes. This results in a significant increase in the similarity between the routing configurations of the modes. In the experimental results it is shown that the number of routing configuration bits that needs to be rewritten is reduced with a factor between 2 and 4 compared to conventional techniques.","PeriodicalId":439122,"journal":{"name":"2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124542291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Recent advances and challenges in physical design automation 物理设计自动化的最新进展和挑战

2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2013-11-07 DOI: 10.1109/ISVLSI.2013.6654613

M. Johann

{"title":"Recent advances and challenges in physical design automation","authors":"M. Johann","doi":"10.1109/ISVLSI.2013.6654613","DOIUrl":"https://doi.org/10.1109/ISVLSI.2013.6654613","url":null,"abstract":"Summary form only given. A key factor that enabled the development of the microelectronics industry was the creation of sophisticated software tools for design automation. The tremendous evolution of manufacturing capacity was primarily fuelled by scaling down the transistors. Thus, besides being possible to integrate an increasing number of devices, they have also become increasingly faster. However, this wonderful manufacturing capacity would be of little use if it were not possible for human designers to specify the different functions, structures and physical characteristics of highly complex projects in a progressively more efficient way. That is why the most traditional design problems such as placement, routing, gate sizing, are still hot topics today. In the last years, all these subjects regained a lot of attention and experimented significant, sometimes radical, advancements. In this talk we review basic concepts at the definition of such problems, which in general require combinatory optimization, and cover some of the most important achievements in placement and routing in the last decade. They were made possible by the combined effort of industry and academia with the release of realistic benchmark sets and the promotion of several research contests. Finally, we can better understand some of the current challenges that must be faced to keep pace with the next big designs, highlighting the relevance of research in this area.","PeriodicalId":439122,"journal":{"name":"2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"11 8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132939391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Distributed resource management in NoC-based MPSoCs with dynamic cluster sizes 动态集群大小的基于noc的mpsoc分布式资源管理

2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2013-11-07 DOI: 10.1109/ISVLSI.2013.6654651

Guilherme M. Castilhos, Marcelo G. Mandelli, G. Madalozzo, F. Moraes

引用次数: 48

Neutron-induced single event effects analysis in a SAR-ADC architecture embedded in a mixed-signal SoC 混合信号SoC中SAR-ADC架构的中子诱导单事件效应分析

2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2013-11-07 DOI: 10.1109/ISVLSI.2013.6654657

L. Tambara, F. Kastensmidt, P. Rech, T. Balen, M. Lubaszewski

引用次数: 8

Design of standard-cell libraries for asynchronous circuits with the ASCEnD flow 用ASCEnD流设计异步电路的标准单元库

2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2013-11-07 DOI: 10.1109/ISVLSI.2013.6654647

Matheus T. Moreira, Ney Laert Vilar Calazans

引用次数: 7

Branch-and-bound style resource constrained scheduling using efficient structure-aware pruning 使用有效的结构感知修剪的分支绑定式资源约束调度

2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2013-11-07 DOI: 10.1109/ISVLSI.2013.6654637

Mingsong Chen, Saijie Huang, G. Pu, P. Mishra

引用次数: 6

LImbiC: An adaptable architecture description language model for developing an application-specific image processor LImbiC:用于开发特定于应用程序的图像处理器的适应性架构描述语言模型

2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2013-11-07 DOI: 10.1109/ISVLSI.2013.6654619

Carsten Tradowsky, T. Harbaum, Shaver Deyerle, J. Becker

{"title":"LImbiC: An adaptable architecture description language model for developing an application-specific image processor","authors":"Carsten Tradowsky, T. Harbaum, Shaver Deyerle, J. Becker","doi":"10.1109/ISVLSI.2013.6654619","DOIUrl":"https://doi.org/10.1109/ISVLSI.2013.6654619","url":null,"abstract":"Due to their ease of integration and widespread adoption, General Purpose Processors (GPP) are presently used in a wide range of applications. However, the highly flexible nature of a GPP leads to overhead in terms of power, performance and area for a specific application. Another approach, proposed by this paper, is to use Application-Specific Instruction-set Processors (ASIP) that are specifically adapted to a given application. To decrease development time and effort and consequently time-to-market, a model-based development process is used. The high-level model allows for automated generation of software development tools, simulation models and RTL models from a single source. An adaptable LISA model representing a simplified ARM Cortex-M1 processor is used as a base, which is then supplemented by application-specific features requested by the software developer or system architect. This paper presents a working example of this concept, in which a state-of-the-art processor model, we call LImbiC, is extended to meet the requirements of a specific application. Specifically, custom instructions are added to the LImbiC processor to improve its performance in the particular task of image processing. In addition, during the development process infrequently used or obsoleted instructions can be removed, which allows for separate versions of LImbiC to meet varying design goals within the design space exploration.","PeriodicalId":439122,"journal":{"name":"2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116228492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

A discussion on SRAM forward/inverse problem analyses for RTN long-tail distributions RTN长尾分布的SRAM正/逆问题分析探讨

2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2013-11-07 DOI: 10.1109/ISVLSI.2013.6654623

Worawit Somha, H. Yamauchi, Ma YuYu

引用次数: 4

A study on polymorphing superscalar processor dynamically to improve power efficiency 动态多态超标量处理器以提高功率效率的研究

2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2013-11-07 DOI: 10.1109/ISVLSI.2013.6654621

S. Srinivasan, Rance Rodrigues, A. Annamalai, I. Koren, S. Kundu

{"title":"A study on polymorphing superscalar processor dynamically to improve power efficiency","authors":"S. Srinivasan, Rance Rodrigues, A. Annamalai, I. Koren, S. Kundu","doi":"10.1109/ISVLSI.2013.6654621","DOIUrl":"https://doi.org/10.1109/ISVLSI.2013.6654621","url":null,"abstract":"Asymmetric Multicore Processors (AMP) have emerged as likely candidates to solve the performance/power conundrum in the current generation of processors. Most recent work in this area evaluate such multicores by considering large (usually out-of-order (OOO)) and small (usually in-order (InO)) cores on the same chip. Dynamic online swapping of threads between these cores is then facilitated whenever deemed beneficial. However, if threads are swapped too often, the overheads may negatively impact the benefits of swapping. Hence, in most recent work, thread swapping decisions are made at coarse grain instruction granularities, leaving out many opportunities. In this paper, we propose a scheme to mitigate the penalty imposed by thread swapping and yet achieve all the benefits of AMPs. Here, a single superscalar OOO core morphs itself into an InO core at runtime, whenever determined to be performance/Watt efficient. Certain Intel processors already have a similar mechanism to statically morph an OOO core to an InO core to facilitate debug. We extend this existing capability to perform dynamic core morphing at runtime with an orthogonal objective of improving power efficiency. Results indicate that on an average, performance/Watt benefits of 10% can be extracted by our proposed morphing scheme at a very small performance penalty of 3.8%. Since this scheme is based on existing mechanisms readily available in current microprocessors, it incurs no hardware overheads.","PeriodicalId":439122,"journal":{"name":"2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131208116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5