2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)最新文献_第5页

Iterative remapping respecting timing constraints 尊重时间约束的迭代重新映射

2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2013-08-01 DOI: 10.1109/ISVLSI.2013.6654639

Lucas Machado, Mayler G. A. Martins, V. Callegaro, Renato P. Ribas, A. Reis

引用次数: 8

Ground gated 8T SRAM cells with enhanced read and hold data stability 接地门控8T SRAM单元具有增强的读取和保持数据稳定性

2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2013-08-01 DOI: 10.1109/ISVLSI.2013.6654622

Hailong Jiao, V. Kursun

引用次数: 11

Exploiting body biasing for leakage reduction: A case study 利用车身偏置减少泄漏:一个案例研究

2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2013-08-01 DOI: 10.1109/ISVLSI.2013.6654635

A. Manuzzato, F. Campi, D. Rossi, V. Liberali, D. Pandini

{"title":"Exploiting body biasing for leakage reduction: A case study","authors":"A. Manuzzato, F. Campi, D. Rossi, V. Liberali, D. Pandini","doi":"10.1109/ISVLSI.2013.6654635","DOIUrl":"https://doi.org/10.1109/ISVLSI.2013.6654635","url":null,"abstract":"In modern System-on-Chip (SoC) designs, the fulfillment of power constraints is one of the most important and challenging tasks. In this framework, the use of both voltage scaling and body biasing techniques is a mainstream strategy largely used for leakage power reduction. This work presents a case study to evaluate the impact of these techniques on an industrial microprocessor-based design. We analyze the impact of body biasing in terms of area penalties and routing efforts. Furthermore, a complete analysis flow is proposed to evaluate the achievable leakage reduction and the expected performance degradation. In order to overcome the limited spectrum of operating configurations covered by a given library set, we propose a practical and effective methodology based on a standard digital design and characterization flow. By using this procedure, a designer can efficiently evaluate the most appropriate leakage/timing trade-offs, and consequently determine the best supply voltage and biasing configurations to implement the design. The experimental results on our testcase demonstrate that body biasing leads to a leakage reduction up to six times with respect to the standard reference supply voltage configuration.","PeriodicalId":439122,"journal":{"name":"2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123664606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Embedded systems design for smart system integration 智能系统集成的嵌入式系统设计

2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2013-08-01 DOI: 10.1109/ISVLSI.2013.6654611

M. Glesner, F. Philipp

{"title":"Embedded systems design for smart system integration","authors":"M. Glesner, F. Philipp","doi":"10.1109/ISVLSI.2013.6654611","DOIUrl":"https://doi.org/10.1109/ISVLSI.2013.6654611","url":null,"abstract":"Summary form only given. Smart or intelligent system is a new technology term that will be found in many applications in our daily life and industries in the future for examples in energy management, medical applications and healthcare management, industrial automation and automotive. Based on its technological term, smart systems should have capabilities to solve very complex problems, including taking over human cognitive functions. Due to the exponential increase of world energy demand, in which between 2010 and 2030 is estimated to be 45%, energy management will be one of the most urgent topics of the century and a significant driver for the evolution of semiconductors and electronics products. The important issues in the energy management are efficiency and reliability. Those requirements initiate the movement of power technology trend from traditional into smart grids concept. Cybersecurity and control systems for instance will be important topics for future smart grid systems. In medical applications and healthcare management, smart products are mainly dedicated to improve the quality of health treatments and rehabilitations. The key components of the products are sensors (biomedical sensors). They should be miniaturized, which is enabled by using Micro-Electro-Mechanical System (MEMS) technology, in order to minimize the physical effect on the biologic system. The key factor of the smart systems is new inventions in the fields of nanotechnology, advanced materials, biotechnology, photonic technology and nanoelectronics. The innovation of efficient computing algorithms should be a challenging issue to implement the nanoelectronic products. The integration of the nanoelectronic products into smart systems should consider both arts and cost aspect. Therefore, the miniaturization of smart products, which is affected by efficient computing algorithms and nano-scale technologies, will be an interesting feature for end-users on market.","PeriodicalId":439122,"journal":{"name":"2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121257465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Comparison between three RTL implementations of the multiplicative inverse calculation of galois field elements based on a standard cells library 基于标准单元库的伽罗瓦域元乘法逆计算的三种RTL实现比较

2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2013-08-01 DOI: 10.1109/ISVLSI.2013.6654660

Otacilio de Araujo Ramos Neto, A. C. Cavalcanti, R. Altafim

{"title":"Comparison between three RTL implementations of the multiplicative inverse calculation of galois field elements based on a standard cells library","authors":"Otacilio de Araujo Ramos Neto, A. C. Cavalcanti, R. Altafim","doi":"10.1109/ISVLSI.2013.6654660","DOIUrl":"https://doi.org/10.1109/ISVLSI.2013.6654660","url":null,"abstract":"Most problems found during implementation of Galois Field (GF) arithmetic in Very-Large-Scale-Integration (VLSI) circuits, are the area occupied by the blocks responsible for the product of two elements and by the calculation of the multiplicative inverse of an element. This last, is the main routine applied on the S-Box and Inv S-Box functions of the Advanced Encryption Standard (AES) Rijndael algorithm. Therefore, on a complete implementation of the AES algorithm in hardware, one may expect that approximate 50% of the circuit area is occupied only with those instances. As an example, a simple pipeline implementation of the Rijndael algorithm may require more than 160 instances of the S-Box blocks, only in the encrypter of a GF (28). Since the multiplicative inverse applied in S-Box or Inv S-Box can be implemented by different methods and they consume considerable space in a VLSI implementation, it is desired to determine the most appropriated solution for VLSI circuits. Therefore, in this work we implemented three different approaches for the calculation of the multiplicative inverse in a GF (28) and map them into digital blocks. The digital blocks were then transcribed into a hardware description language (HDL), converted to Register Transfer Level (RTL) and synthesized over the same standard cells library. A comparison between these implementations regarding the estimated circuit area, the number of clock cycles and the maximum operation frequency, for a GF (28) of the AES are here presented.","PeriodicalId":439122,"journal":{"name":"2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"216 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122120109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Simultaneous gate sizing and Vth assignment using Lagrangian Relaxation and delay sensitivities 利用拉格朗日松弛和延迟灵敏度同时进行栅极尺寸和v值分配

2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2013-08-01 DOI: 10.1109/ISVLSI.2013.6654627

G. Flach, Tiago Reimann, G. Posser, M. Johann, R. Reis

引用次数: 7

Whitespace-aware TSV arrangement in 3D clock tree synthesis 三维时钟树合成中的空白感知TSV排列

2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 1900-01-01 DOI: 10.1109/ISVLSI.2013.6654632

Xin Li, Wulong Liu, Haixiao Du, Yu Wang, Yuchun Ma, Huazhong Yang

引用次数: 4