Exploiting body biasing for leakage reduction: A case study

Abstract

In modern System-on-Chip (SoC) designs, the fulfillment of power constraints is one of the most important and challenging tasks. In this framework, the use of both voltage scaling and body biasing techniques is a mainstream strategy largely used for leakage power reduction. This work presents a case study to evaluate the impact of these techniques on an industrial microprocessor-based design. We analyze the impact of body biasing in terms of area penalties and routing efforts. Furthermore, a complete analysis flow is proposed to evaluate the achievable leakage reduction and the expected performance degradation. In order to overcome the limited spectrum of operating configurations covered by a given library set, we propose a practical and effective methodology based on a standard digital design and characterization flow. By using this procedure, a designer can efficiently evaluate the most appropriate leakage/timing trade-offs, and consequently determine the best supply voltage and biasing configurations to implement the design. The experimental results on our testcase demonstrate that body biasing leads to a leakage reduction up to six times with respect to the standard reference supply voltage configuration.